Memory control system for controlling a buffer memory

Claim 2

A memory control system for a computer having a central processor, a main memory, a buffer memory including a plurality of sectors each consisting of a plurality of blocks, and a memory controller controlling the buffer memory, said memory controller comprising: a plurality of associative registers for operatively holding therein the page addresses in the main memory of information stored in said sectors and also validity indicators pointing out in what block in said sectors valid information is stored; means for comparing more significant bits corresponding to the page address of an address signal supplied from said central processor with the page address held in said associative registers; sector check means for checking whether an output signal showing a coincidence between more significant bits of the address signal and the page addresses is delivered from said comparing means; means for immediately applying a request signal to said buffer memory when said output signal is produced; block check means for checking the validity indicators by less significant bits corresponding to the block of said address signal after applying the request signal to said buffer memory; and means for generating a signal so that the result of processing in said buffer memory carried out upon the above request may not be transferred to said central processor.

Claim 3

A memory control system as claimed in claim 1, in which said associative registers comprise a sector part for storing therein the page address in the main memory of the information stored in said sectors and the validity indicators pointing out the validity of information stored in the blocks in said sectors.

Claim 4

A memory control system as claimed in claim 1, in which said sector check means comprises a check circuit for detecting an output signal from said comparing means showing coincidence between more significant bits of the address signal and the page addresses, and said request signal-applying means comprises a flip-flop adapted to be set by a detecting signal from said check circuit to apply the request signal to said buffer memory.

Claim 5

A memory control system as claimed in claim 1, in which said block check means comprises a decoder for converting the bits corresponding to the block of the address signal supplied from said central processor into a signal pointing out the block, comparators for comparing the decoded signal from said decoder with said validity indicators, and delivering output signals showing whether the decoded signal is coincident with the validity indicators, gate circuits for gating the output signals from said comparators with the output signal delivered from said comparing means, and a check circuit for detecting an output signal showing coincidence between the decoded signal and validity indicators among the output signal from said gate circuits, and wherein said signal-generating means comprises a flip-flop for generating a signal for preventing a data signal from being sent from said buffer memory to said central processor.

Claim 6

A memory control system for a computer having a central processor, a main memory, a buffer memory including a plurality of sectors each consisting of a plurality of blocks and a memory controller for controlling said buffer memory, said memory controller, comprising: a plurality of associative registers for holding therein the page addresses, in said memory, of information stored in said sectors and validity indicators identifying which block in said sectors has valid information stored therein; means, responsive to said registers and said central processor, for comparing the bits corresponding to the page address of an address signal supplied from said central processor with the page addresses held in said associative registers; sector check means responsIve to the output of said comparing means, for generating an output signal when coincidence between first significant bits of the address signal and the page addresses is provided by said comparing means; means, responsive to said output signal produced by said sector check means, for supplying a request signal to said buffer memory; block check means, responsive to the bits less significant than said first significant bits representative of the outputs of said associative registers corresponding to the block of the address signal for checking said validity indicators, after said request signal is supplied to said buffer memory; and means for preventing the result of processing in said buffer memory in response to said request signal from being transferred to said central processor.

Claim 7

A memory control system for a computer having a central processor, a main memory, a buffer memory including a plurality of sectors each consisting of a plurality of blocks and a memory controller for controlling said buffer memory, said memory controller, comprising: a plurality of associative registers for holding therein the page addresses, in said memory, of information stored in said sectors and validity indicators identifying which block in said sectors has valid information stored therein; means, responsive to said registers and said central processor, for comparing the bits corresponding to the page address of an address signal supplied from said central processor with the page addresses held in said associative registers; sector check means responsIve to the output of said comparing means, for generating an output signal when coincidence between first significant bits of the address signal and the page addresses is provided by said comparing means; means, responsive to said output signal produced by said sector check means, for supplying a request signal to said buffer memory; block check means, responsive to the bits less significant than said first significant bits representative of the outputs of said associative registers corresponding to the block of the address signal for checking said validity indicators, after said request signal is supplied to said buffer memory; and means for preventing the result of processing in said buffer memory in response to said request signal from being transferred to said central processor.

Claim 8

A memory control system according to claim 5, wherein said associative registers comprise a sector portion for storing therein the page address in the main memory of the information stored in said sectors and the validity indicators identifying the validity of information stored in the blocks in said sectors.

Claim 9

A memory control system according to claim 6, wherein said sector check means comprises a check circuit for detecting an output signal from said comparing means upon coincidence between said first more significant bits of the address signal and the page addresses, and wherein said request signal-applying means comprises a first flip-flop, adapted to be fed by a detecting signal from said check circuit, for applying the request signal to said buffer memory.

Claim 10

A memory control system according to claim 7, wherein said block check means comprises a decoder for converting the bits corresponding to the block of the address signal supplied from said central processor into a signal identifying the block, comparators for comparing the decoded signal from said decoder with said validity indicators and delivering output signals representative of whether the decoded signal is coincident with the validity indicators, gate circuits for gating the output signals from said comparators with the output signal provided by said comparing means and a check circuit for detecting an output signal showing coincidence between the decoded signal and validity indicators among the output signals from said gate circuits, and wherein said signal-generating generating means comprises a second flip-flop for generating a signal for preventing data from being sent from said buffer memory to said central processor.