Patent US3610906A successfully refreshed from Google Patents.
US3610906A
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Binary multiplication utilizing squaring techniques
Assignee: Unisys Corp
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Filing: 1968-11-07
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Granted: 1971-10-05
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Expires: 1988-11-07
Abstract
Abstract A means and a method of high-speed multiplication are presented which are capable of replacing existing multiplication methods in present day digital data processing systems. In the system disclosed, the two operands may be manipulated in the computer''s arithmetic unit so that the multiplier logic unit need perform only two squaring functions, followed by a subtraction. This latter subtraction function also may be performed by the arithmetic unit of the computer. There are various ways in which this squaring can replace multiplying two different operands. Generally in the preferred method, operands a and b are added together and squared. Next the two original operands are subtracted and squared. Finally the second product is subtracted from the first and effectively divided by four to obtain the result. Variations of this method are more specifically described as they are used in this invention.
Inventors
- 👤 William A Stampler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:58
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/5235; G06F7/544; G06F7/552; G06F2207/00; G06F2207/552; G06F2207/5523
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
A high-speed binary digital-multiplying device comprising an arithmetic unit connected to receive a first and a second operand to be multiplied, a squaring means connected to said arithmetic unit to receive therefrom a pair of identical operands to be multiplied and to provide thereto the squared value of the identical operands, said squaring means including an input register, a plurality of AND gates connected to said input register for producing a plurality of partial products, a onestep adding means connected to said plurality of gates to simultaneously add together said plurality of partial products, further means connected between said plurality of AND gates and said one-step adder for simplifying said partial products prior to said summation by said one-step adder, and an output register connected to said adder to receive and temporarily store the simultaneous summation of said partial products.
Claim 2
Dependent Claim
140 words
A high-speed binary digital-multiplying device comprising an arithmetic unit connected to receive a first and a second operand to be multiplied, a squaring means connected to said arithmetic unit to receive therefrom a pair of identical operands to be multiplied and to provide thereto the squared value of the identical operands, said squaring means including an input register, a plurality of AND gates connected to said input register for producing a plurality of partial products, a onestep adding means connected to said plurality of gates to simultaneously add together said plurality of partial products, further means connected between said plurality of AND gates and said one-step adder for simplifying said partial products prior to said summation by said one-step adder, and an output register connected to said adder to receive and temporarily store the simultaneous summation of said partial products.
Claim 3
Dependent Claim
125 words
A high-speed binary digital-multiplying device for multiplying a first and a second operand comprising an arithmetic means and a squaring means connected thereto, said squaring means including means for producing partial products of said operands and further means connected to said partial product producing means for simplifying said partial products, said arithmetic means including means for supplying to said squaring means the sum of and the difference between said first and said second operands, said arithmetic unit including further means for receiving from said squaring means the squared values of said sum and difference and for subtracting the smaller of said squared values from the larger and for dividing the resulting difference by four and thereby provide the product of said first and second operands.
Claim 4
Dependent Claim
125 words
A high-speed binary digital-multiplying device for multiplying a first and a second operand comprising an arithmetic means and a squaring means connected thereto, said squaring means including means for producing partial products of said operands and further means connected to said partial product producing means for simplifying said partial products, said arithmetic means including means for supplying to said squaring means the sum of and the difference between said first and said second operands, said arithmetic unit including further means for receiving from said squaring means the squared values of said sum and difference and for subtracting the smaller of said squared values from the larger and for dividing the resulting difference by four and thereby provide the product of said first and second operands.
Claim 5
Dependent Claim
89 words
A high-speed binary digital-multiplying device as set forth in claim 2 wherein said squaring means further includes an input register to receive the sum and difference of said first and second operands, said means for producing partial products comprising a plurality of AND gates connected to said input register for producing partial products, a one-step adder commonly connected to said simplifying means to simultaneously add together said simplified partial products and an output register connected to said one-step adder to receive and temporarily store the desired product so produced.
Claim 6
Dependent Claim
89 words
A high-speed binary digital-multiplying device comprising an arithmetic unit capable of receiving a first and a second operand, a logical squaring means connected to said arithmetic unit to provide a one-step squaring operation, said squaring means further including a means for producing, simplifying and adding a plurality of partial products, a one-word temporary storage means also connected to said arithmetic unit, and a separate subtraction unit connected to said squaring means and to said temporary storage means to provide therefrom the product of said first and said second operands.
Claim 7
Dependent Claim
89 words
A high-speed binary digital-multiplying device comprising an arithmetic unit capable of receiving a first and a second operand, a logical squaring means connected to said arithmetic unit to provide a one-step squaring operation, said squaring means further including a means for producing, simplifying and adding a plurality of partial products, a one-word temporary storage means also connected to said arithmetic unit, and a separate subtraction unit connected to said squaring means and to said temporary storage means to provide therefrom the product of said first and said second operands.
Claim 8
Dependent Claim
101 words
A high-speed binary digital-multiplying device for producing the product of a pair of identical operands, comprising an input register, a plurality of gates connected to said input register to produce a plurality of partial products, a one-step adder commonly connected to said plurality of gates to simultaneously add together said plurality of partial products, a means connected between said plurality of gates and said one-step adder to simplify said plurality of partial products prior to their simultaneous addition by said adder, and an output register connected to said one-step adder to store the squared product of said pair of identical operands.
Claim 9
Dependent Claim
101 words
A high-speed binary digital-multiplying device for producing the product of a pair of identical operands, comprising an input register, a plurality of gates connected to said input register to produce a plurality of partial products, a one-step adder commonly connected to said plurality of gates to simultaneously add together said plurality of partial products, a means connected between said plurality of gates and said one-step adder to simplify said plurality of partial products prior to their simultaneous addition by said adder, and an output register connected to said one-step adder to store the squared product of said pair of identical operands.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |