Patent US3609756A successfully refreshed from Google Patents.
US3609756A
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Devices for producing output signals in digital form
Assignee: Imperial Chemical Industries Ltd
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Filing: 1969-05-19
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Granted: 1971-09-28
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Expires: 1989-05-19
Abstract
Abstract A frequency-to-digital converter for producing continuously available output signals in digital form including a pulse counter which produces an output in Gray code, a binary pulse rate multiplier coupled to the counter and a frequency comparator for receiving the input frequency signals to the converter, receiving feedback signal in pulse form form the multiplier, and supplying output signals to the first counter, the repetition rate of the feedback signals being proportional to the Gray code output of the first counter, so that the output of the first counter in Gray code forms the output of the converter in digital form.
Inventors
- 👤 James Richard Halsall
- 👤 Alan Percy Cooper Murrell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:54
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03K; H03K21/00; H03M; H03M1/00; H03M1/12; H03M1/18; H03M1/181; H03M1/182; H03M1/60
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
267 words
A frequency to digital converter for producing continuously available output signals in digital form comprising: a. a first pulse counter which comprises a plurality of bistable elements arranged to produce an output in Gray code and suitably connected to a plurality of Exclusive-OR logic elements for converting the Gray code output to a binary code output, means for generating a parity signal from the binary code output to represent the parity of the Gray code output, and means for applying the parity signal to the plurality of bistable elements; b. a binary pulse rate multiplier, directly coupled to the first counter, which comprises a plurality of further bistable elements arranged to operate as a second Gray code pulse counter, and means whereby the pulses arriving at the inputs to the further bistable elements are routed to a combined output pulse line via separate respective pulse rate selection gates, so that energization of appropriate ones of the selection gates creates an output pulse train in the output pulse line having an average repetition rate which is a desired fraction of the average repetition rate of the input pulses applied to the second counter by way of an input pulse line; c. a frequency comparator for receiving the input frequency signals to the converter, receiving feedback signals in pulse form from the multiplier, and supplying output signals to the first counter, the repetition rate of the feedback signals being proportional to the Gray code output of the first counter, so that the output of the first counter in Gray code forms the output of the converter in digital form.
Claim 2
Dependent Claim
267 words
A frequency to digital converter for producing continuously available output signals in digital form comprising: a. a first pulse counter which comprises a plurality of bistable elements arranged to produce an output in Gray code and suitably connected to a plurality of Exclusive-OR logic elements for converting the Gray code output to a binary code output, means for generating a parity signal from the binary code output to represent the parity of the Gray code output, and means for applying the parity signal to the plurality of bistable elements; b. a binary pulse rate multiplier, directly coupled to the first counter, which comprises a plurality of further bistable elements arranged to operate as a second Gray code pulse counter, and means whereby the pulses arriving at the inputs to the further bistable elements are routed to a combined output pulse line via separate respective pulse rate selection gates, so that energization of appropriate ones of the selection gates creates an output pulse train in the output pulse line having an average repetition rate which is a desired fraction of the average repetition rate of the input pulses applied to the second counter by way of an input pulse line; c. a frequency comparator for receiving the input frequency signals to the converter, receiving feedback signals in pulse form from the multiplier, and supplying output signals to the first counter, the repetition rate of the feedback signals being proportional to the Gray code output of the first counter, so that the output of the first counter in Gray code forms the output of the converter in digital form.
Claim 3
Dependent Claim
73 words
A converter according to claim 1, wherein the input frequency signal is compared with a plurality of feedback frequency signals in the comparator so as to produce a continuously available output frequency signal from the comparator of a predetermined range from zero to a maximum value for supply to the first counter, and the output frequency signal from the comparator corresponding to zero indicated output at the first counter has a finite value.
Claim 4
Dependent Claim
21 words
A converter according to claim 2, wherein said plurality of feedback frequencies are derived from the multiplier of a polyphase type.
Claim 5
Dependent Claim
18 words
A converter according to claim 2, wherein said plurality of feedback frequencies are derived from an external source.
Claim 6
Dependent Claim
19 words
A converter according to claim 1, wherein the bistable elements in each said counter are respectively connected in cascade.
Claim 7
Dependent Claim
55 words
A converter according to claim 5, wherein each said counter comprises a plurality of stages, each stage including a said bistable element and interconnected with the next stage through an intermediate logic circuit, each intermediate logic circuit being connected in circuit with a common pulse line and with each other through a direction control line.
Claim 8
Dependent Claim
131 words
A converter according to claim 1, wherein the multiplier is fed by a polyphase clock pulse generator, and wherein one clock phase drives the second counter and produces output pulse trains in the same manner as in the single phase binary rate multiplier, and each additional clock phase is applied to a separate additional set of gates which are also controlled by the same switching signals as the gates fed directly from the outputs of the respective bistable elements but which are not connected to the counter pulse line, so that each of the additional gates provides a further binary pulse rate output from each stage of the second counter which is in phase with a respective additional clock phase, and the multiplier provides polyphase outputs having individual controlled binary rates.
Claim 9
Dependent Claim
35 words
A converter according to claim 6, wherein each said intermediate logic circuit produces a logical output of ''''0'''' when all its inputs are ''''1'''' and a logical output of ''''1'''' under any other input condition.
Claim 10
Dependent Claim
44 words
A converter according to claim 1, wherein the bistable elements of said counters are arranged in stages and wherein the second and up to and including the penultimate stages in each said counter are identical so that the number of stages can be extended.
Claim 11
Dependent Claim
53 words
A converter according to claim 9, wherein the bistable element in the first stage of the first counter is controlled by the parity state and the input pulse and wherein the second and higher stages are each controlled by the parity state, the pulse input and the state of all the preceding stages.
Claim 12
Dependent Claim
48 words
A converter according to claim 1, wherein the bistable elements in each said counter are of the master-slave type which delay a change in the output stage until termination of the initiating input thereby preventing any input causing more than one change in the state of the counter.
Claim 13
Dependent Claim
36 words
A converter according to claim 10, wherein additive pulses beyond a maximum number of subtractive pulses below zero are inhibited by parity control of gating circuits in the first counter thereby preventing overflow in either direction.
Claim 14
Dependent Claim
36 words
A converter according to claim 10, wherein overflow and continuous counting is permitted in the first counter which includes an additional bistable element operable to transmit a signal which causes the first counter to reverse operation.
Claim 15
Dependent Claim
78 words
A converter according to claim 12, wherein the additional bistable element in the first counter is connected in circuit with an additional intermediate logic circuit which receives input signals from the common pulse line and the intermediate logic circuit of the previous stage and wherein the output of the additional bistable is a direction control signal connected to the direction control line through a direction control unit which also receives the parity signal from the binary code output.
Claim 16
Dependent Claim
77 words
A converter according to claim 13, wherEin the first counter is connected in circuit with at least one additional counter, and the direction control signal from the additional bistable of the first counter is fed to the said additional counter which is connected in parallel and which receives signals from the input pulse line, whereby the first counter and the additional counter will be in synchronism on and after the first counter has generated a second reversal.
Claim 17
Dependent Claim
48 words
A converter according to claim 1, wherein the gates from the input pulse line to the inputs of each of the bistable elements of the second counter, except the first bistable element or flip-flop, are controlled by the states of all previous bistable elements of the second counter.
Claim 18
Dependent Claim
35 words
A converter according to claim 16, wherein each of the additional gates has an extra input terminal so that they can be used also as pulse rate selection gates for the appropriate phase combined output.
Claim 19
Dependent Claim
24 words
A frequency to digital converter according to claim 1, wherein the circuits elements used in the multiplier consist of resistors, semiconducting diodes and transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |