Programmed arrangement for serial handling of numerical information

Claim 1

In an apparatus for handling a plurality of data words wherein each data word in comprised of a predetermined number of decimal digits, and each decimal digit is represented in said apparatus by signals indicative of a predetermined number of binary bits, the combination comprising: a dynamic memory having a serial binary input and a serial binary output; an arithmetic unit including a binary serial adder-subtractor means, and a shift register having a plurality of stages equal in number to said predetermined number of binary bits and having a serial binary input and a serial binary output; said adder-subtractor means having a first binary bit input, a second binary bit input, and a binary bit output, said addersubtractor means being responsive to binary bits at its inputs to furnish immediately a result binary bit at its output, said adder-subtractor means being selectively operable to furnish at its output a binary bit representative of the arithmetic sum of binary bits furnished to its inputs, and to furnish at its output a binary bit representative of the arithmetic difference resulting from a binary bit at said second input being subtracted from a binary bit at said first input; memory input data flow means selectively operable between a first condition wherein said shift register output is coupled with said memory input, and a second condition wherein said adder-subtractor means output is coupled with said memory input; means coupling said shift register output with said first input of said adder-subtractor means; shift register input data means selectively operable between a first condition wherein said memory output is coupled with said shift register input, and a second position wherein said addersubtractor means output is coupled with said shift register input; means coupling said memory output with said second input of said adder-subtractor means; said memory input means and said shift register input means operable in a predetermined sequence wherein a first data word is read from said memory into said shift register and written back onto said memory without change, and a second data word is read from said memory into said adder-subtractor means, arithmetically combined with said first data word therein and the results of such arithmetic combining being written into said memory in the location formerly occupied by said second data word; said operable sequence taking the same time as a second operable sequence wherein all data words are read from said memory through said shift register and back onto said memory without change.