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US3609682A
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Augmented digital-error-correcting decoder
Assignee: General Electric Co
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Filing: 1969-07-16
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Granted: 1971-09-28
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Expires: 1989-07-16
Abstract
Abstract An error correcting decoder circuit for decoding redundantly coded received digital signals. Estimator bits are generated from selected bits of a received code word, and estimator reliability signals are generated in accordance with word-bit error probability signals derived from the received analog signal amplitudes associated with the same selected bits of the code word as are used for generating the estimator bits. The estimator reliability signals are used as a basis for weighting the bipolar estimator bit voltages, by increasing or decreasing their absolute values, whereby the more reliable estimator bits are given greater weights at the input of a threshold decision circuit. The threshold decision circuit generates an output bit in accordance with the arithmetic sum of the weighted estimator bit voltages, except that it substitutes the appropriate received bit in place of the unreliable threshold decision that arises in the event that the sum is small in magnitude. Control circuitry is provided for causing repetitive shifting of the word bits in a first shift register and of word-bit error probability signals in a second shift register, for performing step-by-step decoding of a received word with the aid of the received signal reliability indications. The invention thus provides a means of augmenting the digital error correction capability of decoders through the use of auxiliary outputs from the receiver which indicate the received signal quality.
Inventors
- 👤 Michael E Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:19
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H03; H03M; H03M13/00; H03M13/37; H03M13/45; H03M13/458
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
127 words
An error-correcting decoder circuit for decoding a received signal voltage representing a coded word made up of data bits and redundant bits, comprising means for deriving said word bits from said signal voltage, means for generating a plurality of estimator bits from selected bits of said coded word, and decision means for generating a decoded data bit with the aid of said estimator bits, wherein the improvement comprises means for providing a plurality of reliability signals in accordance with the amplitudes oF said voltage from which selected bits of the coded word are derived, and weighting means connected to apply weighting factors to said estimator bits in accordance with said reliability signals, respectively, whereby the more reliable estimator bits are given greater weights in said decision means.
Claim 2
Dependent Claim
127 words
An error-correcting decoder circuit for decoding a received signal voltage representing a coded word made up of data bits and redundant bits, comprising means for deriving said word bits from said signal voltage, means for generating a plurality of estimator bits from selected bits of said coded word, and decision means for generating a decoded data bit with the aid of said estimator bits, wherein the improvement comprises means for providing a plurality of reliability signals in accordance with the amplitudes oF said voltage from which selected bits of the coded word are derived, and weighting means connected to apply weighting factors to said estimator bits in accordance with said reliability signals, respectively, whereby the more reliable estimator bits are given greater weights in said decision means.
Claim 3
Dependent Claim
39 words
A decoder circuit as claimed in claim 1, in which said weighting means comprises a plurality of arithmetic multipliers respectively interposed in the paths of said estimator bits and having multiplier inputs respectively connected to receive said reliability signals.
Claim 4
Dependent Claim
59 words
A decoder circuit as claimed in claim 2, in which the reliability signals derived from relatively low amplitudes of said voltage from which said selected bits of the code word are derived have values such that when applied to said arithmetic multipliers the respective estimator bits are given zero weight and hence are not utilized by said decision means.
Claim 5
Dependent Claim
96 words
A decoder circuit as claimed in claim 1, including first and second shift registers, means for loading said first shift register with the bits of said coded word, means for loading said second shift register with error probability signals derived from the amplitudes of said voltage from which said word bits are derived, a plurality of means each connected to selected stages of said first shift register for generating said plurality of estimator bits, and a plurality of means each connected to selected stages of said second shift register for providing said plurality of reliability signals.
Claim 6
Dependent Claim
70 words
A decoder circuit as claimed in claim 4, in which said selected stages of the second shift register correspond to said selected stages of the first shift register, and in which said reliability signals are applied to said weighting means so as to respectively cause weighting of the estimator bits that are derived from the same said selected shift register stages as those from which the reliability signals are derived.
Claim 7
Dependent Claim
55 words
A decoder circuit as claimed in claim 4, in which said means for loading said second shift register includes conversion means for converting the amplitude of said voltage from which the word bits are derived into a plurality of discrete voltage signals on one or more signal conductors for loading into said second shift register.
Claim 8
Dependent Claim
46 words
A decoder circuit as claimed in claim 6, in which said conversion means comprises a null zone detector adapted to produce alternative output voltage signals indicative of whether said amplitude of the voltage from which the word bits are derived is relatively large or relatively small.
Claim 9
Dependent Claim
99 words
A decoder circuit as claimed in claim 4, including means for sequentially shifting said shift registers for the sequential decoding of data bits from a coded word, feedback means connected around said second shift register for selectively causing either circulation or replacement of said error probability signals therein, quality-indicating means for indicating the error probability of the decoded bits, and quality control means connected to said feedback means of said second shift register, said control means being responsive to said quality-indicating means and adapted to generate and feed to the input of the shift register an error probability signal.
Claim 10
Dependent Claim
137 words
A decoder circuit as claimed in claim 8, including an arithmetic adder connected to produce an output signal derived from said estimator bits, and in which said quality-indicating means comprises a null zone detector connected to the output of said arithmetic adder, and in which said control means connected to said feedback means of the second shift register comprises an AND gate. 10. A decoder circuit as claimed in claim 8, including an adaptive control means connected to said quality control means and adapted to detect the frequent occurrence of error probability signals indicative of a poor decision quality, and switching means adapted to selectively connect a direct feedback path from the output stage to input stage of one or both of said shift registers upon the occurrence of said last-named detection by the adaptive control means.
Claim 11
Dependent Claim
33 words
A decoder circuit as claimed in claim 4, including switching means connected to selectively connect the output stage of said first shift register to the input stage thereof, thereby providing a feedback path.
Claim 12
Dependent Claim
33 words
A decoder circuit as claimed in claim 4, including switching means connected to selectively connect the output stage of said second shift register to the input stage thereof, thereby providing a feedback path.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |