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US3609665A
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Apparatus for exchanging information between a high-speed memory and a low-speed memory
Assignee: Unisys Corp
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Filing: 1970-03-19
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Granted: 1971-09-28
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Expires: 1990-03-19
Abstract
Abstract Data is exchanged between a high-speed memory and a plurality of low-speed memories at the speed of the high-speed memory by timesharing a group of low-speed memories. During each Read-Write cycle of the high-speed memory, data is transferred from one of the low-speed memories to the high-speed memory during the Read operation of the high-speed memory cycle and transferred from the high-speed memory to the low-speed memory during the following Write operation of the high-speed memory. Both transfers take place between the Read operation and Write operation of the ReadWrite cycle of the low-speed memory. By overlapping in time the Read-Write cycles of the low-speed memories, the exchange transfer takes place at a rate determined by the Read-Write cycle time of the high-speed memory.
Inventors
- 👤 Reinhard K Kronies
- 👤 Iver C Hansen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G11; G11B; G11B5/00; G11B5/02; G11B5/09
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
227 words
Apparatus for exchanging data between two storage devices comprising a high-speed addressable memory, including an input register, an output register, an address register, and control means for causing the memory to sequentially read out the information from the location specified by the address register into the output register and write information into the same location from the input register during one memory cycle, a lowspeed addressable memory including an input register, an output register, an address register, and control means for causing the memory to sequentially read out information from the location specified by the address register into the output register and write information into the same location from the input register during one memory cycle, first means for transferring information from the output register of the low-speed memory to the input register of the high-speed memory, second means for transferring information from the output register of the high-speed memory to the input register of the low-speed memory, control means activating said first transferring means during the read portion of a high-speed memory cycle and activating the second transferring means during the write portion of the same highspeed memory cycle, and means synchronizing the high speed memory cycle with the low-speed memory cycle such that the high-speed memory cycle occurs between the completion of the read portion and start the write portion of the low-speed memory cycle.
Claim 2
Dependent Claim
227 words
Apparatus for exchanging data between two storage devices comprising a high-speed addressable memory, including an input register, an output register, an address register, and control means for causing the memory to sequentially read out the information from the location specified by the address register into the output register and write information into the same location from the input register during one memory cycle, a lowspeed addressable memory including an input register, an output register, an address register, and control means for causing the memory to sequentially read out information from the location specified by the address register into the output register and write information into the same location from the input register during one memory cycle, first means for transferring information from the output register of the low-speed memory to the input register of the high-speed memory, second means for transferring information from the output register of the high-speed memory to the input register of the low-speed memory, control means activating said first transferring means during the read portion of a high-speed memory cycle and activating the second transferring means during the write portion of the same highspeed memory cycle, and means synchronizing the high speed memory cycle with the low-speed memory cycle such that the high-speed memory cycle occurs between the completion of the read portion and start the write portion of the low-speed memory cycle.
Claim 3
Dependent Claim
50 words
Apparatus as defined in claim 1 further comprising additional low-speed memories, switching means for switching said first and second transferring means to the input and output registers of each of the low-speed memories in sequence, and means for synchronizing the switching means with the start of each high-speed memory cycle.
Claim 4
Dependent Claim
30 words
Apparatus as defined in claim 2 including means initiating memory cycles in the low-speed memories in sequence at spaced intervals corresponding to the time duration of a high-speed memory cycle.
Claim 5
Dependent Claim
23 words
Apparatus as defined in claim 3 including means changing the address in each address register with each memory cycle of the associated memory.
Claim 6
Dependent Claim
29 words
Apparatus as defined in claim 3 wherein the number of low-speed memories is equal to the ratio of the low-speed memory cycle time to the high-speed memory cycle time.
Claim 7
Dependent Claim
51 words
Apparatus as defined in claim 2 wherein the control means of each of the low-speed memories provides a delay interval between the end of the read and start of the write portions of the memory cycle, said delay interval being substantially equal to the memory cycle time of the high-speed memory.
Claim 8
Dependent Claim
175 words
Apparatus for exchanging information in a digital storage register comprising an addressable high-speed memory having a read-write memory cycle, a plurality of low-speed memories each having a read-write memory cycle, the memory cycle of the low-speed memories having an idle period between the read and write portions of the cycle, first control means for continuously recycling the high-speed memory including means for addressing a different location in memory with each memory cycle, second control means for continuously recycling each of the low-speed memories including means for addressing a different location in each memory with each memory cycle of that memory, said second control means including delay means for starting the low-speed memory cycles sequentially at intervals corresponding to the time of one memory cycle of the high-speed memory, first means transferring a word from a low-speed memory to the high-speed memory during the read portion of a high-speed memory cycle, and 170 second means transferring a word from the high-speed memory to the same low-speed memory during the write portion of same high-speed memory cycLe.
Claim 9
Dependent Claim
175 words
Apparatus for exchanging information in a digital storage register comprising an addressable high-speed memory having a read-write memory cycle, a plurality of low-speed memories each having a read-write memory cycle, the memory cycle of the low-speed memories having an idle period between the read and write portions of the cycle, first control means for continuously recycling the high-speed memory including means for addressing a different location in memory with each memory cycle, second control means for continuously recycling each of the low-speed memories including means for addressing a different location in each memory with each memory cycle of that memory, said second control means including delay means for starting the low-speed memory cycles sequentially at intervals corresponding to the time of one memory cycle of the high-speed memory, first means transferring a word from a low-speed memory to the high-speed memory during the read portion of a high-speed memory cycle, and 170 second means transferring a word from the high-speed memory to the same low-speed memory during the write portion of same high-speed memory cycLe.
Claim 10
Dependent Claim
34 words
Apparatus as defined in claim 7 further including means connecting the first and second transferring means to each low-speed memory in sequence during the idle period of the memory cycle of each low-speed memory.
Claim 11
Dependent Claim
229 words
Information swapping apparatus for exchanging digital words between two addressable random access memory units during one memory cycle of both units where the memory cycle of each unit includes a read portion for reading out the word stored in a particular address location followed by a write portion for writing in a word into the same address location, said apparatus comprising first and second registers, means reading a word from a predetermined address in the first memory unit into the first register in response to the read portion of a memory cycle of the first memory unit, means reading a word from a predetermined address in the second memory unit into the second register in response to the read portion of a memory cycle of the second memory unit, means writing the word in the first register into the same address location in the second memory unit in response to the write portion of the same memory cycle of the second memory unit, means writing the word in the second register into the same address location in the first memory unit in response to the write portion of the same memory cycle of the first memory unit, and means synchronizing the memory cycles of the two memory units such that the transition from the read to the write portions of the memory cycles of both memory units are coincident.
Claim 12
Dependent Claim
229 words
Information swapping apparatus for exchanging digital words between two addressable random access memory units during one memory cycle of both units where the memory cycle of each unit includes a read portion for reading out the word stored in a particular address location followed by a write portion for writing in a word into the same address location, said apparatus comprising first and second registers, means reading a word from a predetermined address in the first memory unit into the first register in response to the read portion of a memory cycle of the first memory unit, means reading a word from a predetermined address in the second memory unit into the second register in response to the read portion of a memory cycle of the second memory unit, means writing the word in the first register into the same address location in the second memory unit in response to the write portion of the same memory cycle of the second memory unit, means writing the word in the second register into the same address location in the first memory unit in response to the write portion of the same memory cycle of the first memory unit, and means synchronizing the memory cycles of the two memory units such that the transition from the read to the write portions of the memory cycles of both memory units are coincident.
Claim 13
Dependent Claim
32 words
Apparatus as defined in claim 9 wherein the memory cycle of the first memory unit has a period substantially longer in time duration than the memory cycle of the second memory unit.
Claim 14
Dependent Claim
48 words
Apparatus as defined in claim 10 wherein the first memory unit has delay time between the end of the Read portion of the memory cycle and the start of the Write portion that is substantially equal to the period of one memory cycle of the second memory unit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |