Multiaperture ferrite residue arithmetic unit

Claim 2

A residue arithmetic unit comprising a plurality of multiaperture magnetic devices, a level of AND gates, each AND gate being arranged on only one aperture of a first one of the multiaperture magnetic devices, a level of OR gates connected to the AND gates, each OR gate being arranged on only one aperture of a second one of the multiaperture magnetic devices, means for producing first, second, and third control signals, means for applying the first and the second control signals to the first multiaperture magnetic device respectively for storing information in said AND gates of said first device and for clearing information from said AND gates of said first device, and means for applying the second and the third control signals to the second multiaperture magnetic device respectively for storing information in said OR gates of said second device and for clearing information from said OR gates of said second device.

Claim 3

A residue arithmetic unit in accordance with claim 1 further comprising first means for applying a group of input signals in one-out-of-mi codes, representing a first residue number in a plurality of moduli mi, to the AND gates, second means for applying a group of input signals in the one-out-of-mi codes, representing a second residue number in the same moduli mi, to the AND gates, and means including the OR gates for producing a group of output signals in the one-out-of-m1 codes, representing a predetermined residue number in the same plurality of moduli mi, in response to a complete cycle of the first, second, and third control signals.

Claim 4

A data processor comprising a first source producing a first group of pulses in one-out-of-mi codes, representing a first input number in a plurality of moduli mi, where i identifies relatively prime radices, a second source producing a second group of pulses in the one-out-of-mi codes, representing a second input number in the same plurality of moduli mi, magnetic circuit means comprising first, second, and third magnetic structures each structure including a plurality of balanced magnetic apertures, the first structure further comprising a level of AND gates, each AND gate being arranged on an individual aperture of said first structure, means responsive to signals from said first and second sources for storing information about said apertures of said AND gates, and means for clearing said stored information from said apertures of said AND gates, the second structure further comprising a level of buffer circuits, each buffer circuit being arranged on an individual aperture of said second structure, means responsive to signals being stored in said AND gates for storing information about said apertures of said buffer circuits, and means for clearing said stored information from said apertures of said buffer circuits, the third structure further comprising a level of OR gates, each OR gate being arranged on an individual aperture of said third structure, means rEsponsive to information cleared from said AND gates for storing information about said apertures of said OR gates, and means for clearing information from said apertures of said OR gates for producing an output signal representing a predetermined number in the same plurality of moduli mi, and clock means applying first, second and third control signals to the first, second, and third structures.

Claim 5

A data processor comprising a first source producing a first group of pulses in one-out-of-mi codes, representing a first input number in a plurality of moduli mi, where i identifies relatively prime radices, a second source producing a second group of pulses in the one-out-of-mi codes, representing a second input number in the same plurality of moduli mi, magnetic circuit means comprising first, second, and third magnetic structures each structure including a plurality of balanced magnetic apertures, the first structure further comprising a level of AND gates, each AND gate being arranged on an individual aperture of said first structure, means responsive to signals from said first and second sources for storing information about said apertures of said AND gates, and means for clearing said stored information from said apertures of said AND gates, the second structure further comprising a level of buffer circuits, each buffer circuit being arranged on an individual aperture of said second structure, means responsive to signals being stored in said AND gates for storing information about said apertures of said buffer circuits, and means for clearing said stored information from said apertures of said buffer circuits, the third structure further comprising a level of OR gates, each OR gate being arranged on an individual aperture of said third structure, means rEsponsive to information cleared from said AND gates for storing information about said apertures of said OR gates, and means for clearing information from said apertures of said OR gates for producing an output signal representing a predetermined number in the same plurality of moduli mi, and clock means applying first, second and third control signals to the first, second, and third structures.

Claim 6

A data processor in accordance with claim 3 further comprising means including the first structure and responsive to the first control signal for storing in the first structure information from the first and second sources, means including the second structure and responsive to the first control signal for storing in the second structure the same information being stored in the first structure, means including the first structure and responsive to the second control signal for clearing information from the first structure, means including the third structure and responsive to the second control signal for storing in the third structure information cleared from the first structure, means including the third structure and responsive to the third control signal for clearing information from the third structure, means including the third structure and responsive to the third control signal for sending erroneous signals from the third structure toward the first structure, and means including the second structure and responsive to the third control signal and information stored in the second structure for generating signals opposing the erroneous signals from the third structure.

Claim 7

A data processor in accordance with claim 4 further comprising means for applying bias signals of a first polarity to apertures of the first structure, and means for applying bias signals of a second polarity to apertures of the second structure.

Claim 8

A data processor in accordance with claim 5 in which the level of OR gates comprises means producing a group of output pulses representing a residue product of the first and second input numbers.

Claim 9

A data processor in accordance with claim 5 in which the level of OR gates comprises means producing a group of output pulses representing a residue difference between the first and second input numbers.

Claim 10

A data processor in accordance with claim 5 in which the level of AND gates and the level of OR gates both comprise means producing output pulses having magnitudes equal to or greater than magnitudes of the first and second groups of pulses.