Bistable device storage cell

Claim 1

In a matrix of bistable memory cells each addressed by the selection a plurality of lines out of a grid of addressing lines, storage cells each comprising: a. two control rectifiers each having four zones of alternating conductivity and a plurality of cathodes; b. means cross-connecting the intermediate zones of said control rectifiers for maintaining one of the control rectifiers nonconducting when the other control rectifier conducts; c. a first word line means coupled to the anodes of both said control rectifiers for supplying two levels of potential to said anodes, one higher level of potential while the storage cell is being addressed for reading or writing and a lower level of potential while the storage cell is merely storing data; d. a second word line means coupled to one of the cathodes of each of the control rectifiers for supplying two levels of potential to those two cathodes, a higher level of potential while data is being written or read in the storage cell and the lower level of potential while data is merely being stored in the storage cell; and e. separate bit line means connected to the other cathode of each control rectifier for supplying at least two levels of potential to that cathode independently of the potential supplied by the bit and word lines to the other three cathodes of the control rectifiers, one lower level of potential while the storage cell is being addressed for reading or is merely storing information and a higher level of potential when the particular control rectifier is to be turned off in the course of writing data into the storage cell.