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Patent US3603816A successfully refreshed from Google Patents.
US3603816A
Expired / Lapsed
US
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High speed digital circuits
Assignee: Bunker Ramo Corp
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Filing: 1968-08-09
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Granted: 1971-09-07
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Expires: 1988-08-09
Abstract
Abstract Apparatus is provided in digital data equipment for transferring a binary signal to a flip-flop, and deriving therefrom a buffered output signal representing the state into which said flip-flop is being switched by anticipation means coupling the input terminal of the flip-flop to a buffer amplifier driven by the flip-flop. A multibranch, multistage selector tree is employed to selectively couple one of a number of binary signals to the flip-flop. The anticipation means and selector tree overcome and minimize the limitations in switching speeds inherent in such apparatus implemented with insulated-gate, field-effect transistors in an integrated circuit. Switching speed of the flip-flop is increased by the combination of (1) a push-pull arrangement such that when a binary signal is applied to one side the complement of the binary signal is applied to the other side, and (2) an anticipation circuit temporarily shunting current around a load resistor in series with a given one of two cross-coupled active elements.
Inventors
- 👤 George V Podraza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:09
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356026; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01742
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
161 words
In digital data equipment, apparatus for transferring a binary signal at a data input terminal connected to a synchronized flip-flop, and for deriving a buffered output therefrom, comprising: means for transferring clock pulses to a synchronizing input terminal of said flip-flop for switching the flip-flop from a given state to another in response to said binary signal upon the occurrence of a clock pulse; a buffer amplifier having a control terminal connected to said flip-flop for producing at a buffer output terminal a signal representing the state of said flip-flop; and coupling means coupling said data input terminal to said buffer amplifier as well as to said flip-flop so that said binary signal is simultaneously applied to both for initiating switching of said flip-flop while producing at said buffer output terminal a signal corresponding to the state into which said flip-flop is being switched by said binary signal, whereby said buffered output is provided while said flip-flop is being synchronously switched.
Claim 2
Dependent Claim
161 words
In digital data equipment, apparatus for transferring a binary signal at a data input terminal connected to a synchronized flip-flop, and for deriving a buffered output therefrom, comprising: means for transferring clock pulses to a synchronizing input terminal of said flip-flop for switching the flip-flop from a given state to another in response to said binary signal upon the occurrence of a clock pulse; a buffer amplifier having a control terminal connected to said flip-flop for producing at a buffer output terminal a signal representing the state of said flip-flop; and coupling means coupling said data input terminal to said buffer amplifier as well as to said flip-flop so that said binary signal is simultaneously applied to both for initiating switching of said flip-flop while producing at said buffer output terminal a signal corresponding to the state into which said flip-flop is being switched by said binary signal, whereby said buffered output is provided while said flip-flop is being synchronously switched.
Claim 3
Dependent Claim
27 words
Apparatus as defined in claim 1 including means for selectively coupling one of a number of binary signals to said flip-flop comprising a multibranch, multistage selector tree.
Claim 4
Dependent Claim
46 words
Apparatus as defined in claim 2 wherein said selector tree is comprised of insulated-gate, field-effect transistors, whereby stray capacitance is provided at an output switching node thereof by a number of branches connected thereto, said number of branches being less than said number of binary signals.
Claim 5
Dependent Claim
117 words
Apparatus as defined in claim 1 wherein said buffer amplifier comprises a pair of transistors connected in series between a supply voltage source and a source of reference potential, at least one of said transistors being connected to said flip-flop to provide, at a junction between said pair of transistors, a signal corresponding to said binary signal, said junction being connected to said output terminal, and wherein said coupling means includes transistor switching means for synchRonizing production at said junction of a signal corresponding to the state into which said flip-flop is being switched by said binary signal while transfer of said binary signal into said flip-flop is taking place in response to a transfer clock pulse.
Claim 6
Dependent Claim
62 words
Apparatus as defined in claim 4 wherein said transistor switching means comprises: a pair of series-connected transistors connected in parallel with one of said pair of transistors; means connecting said data input terminal to a control terminal of one of said series-connected transistors; and means connecting said synchronizing input terminal to a control terminal of the other one of said series-connected transistors.
Claim 7
Dependent Claim
23 words
Apparatus as defined in claim 5 wherein said transistors are insulated-gate, field-effect transistors, and said control terminals are terminals connected to gates thereof.
Claim 8
Dependent Claim
96 words
Apparatus as defined in claim 1 wherein said buffer amplifier comprises a pair of transistors connected to receive complementary output signals from said flip-flop and provide, at a junction therebetween connected to said output terminal, a signal corresponding to said binary signal, and said coupling means comprises third and fourth series-connected transistors in parallel with one of said pair of transistors, a control terminal of one of said series-connected transistors being connected to said data input terminal and a control terminal of the other one of said series-connected transistors being connected to said synchronizing input terminal.
Claim 9
Dependent Claim
65 words
Apparatus as defined in claim 7 wherein said coupling means further comprises fifth and sixth series-connected transistors in parallel with the other of said pair of transistors, a control terminal of one of said series-connected transistors being connected to receive the complement of said binary signal and a control terminal of the other one of said series-connected transistors being connected to said synchronizing input terminal.
Claim 10
Dependent Claim
23 words
Apparatus as defined in claim 8 wherein said transistors are insulated-gate, field-effect transistors and said control terminals are terminals connected to gates thereof.
Claim 11
Dependent Claim
29 words
Apparatus as defined in claim 8 including means for selectively coupling one of a number of binary signals to said data input terminal comprising a multibranch, multistage selector tree.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |