Patent US3603815A successfully refreshed from Google Patents.
US3603815A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bistable circuits
Assignee: US Philips Corp
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Filing: 1968-04-30
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Granted: 1971-09-07
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Expires: 1988-04-30
Abstract
Abstract An additional AND-gate connected to the clock pulse input of a J-K flip-flop provides an inhibiting input to each of the J and K input AND-gates in response to a clock pulse received before a flip-flop switching input is applied to the J-K input gates. The inhibiting input prevents the flip-flop from reversing state in response to a switching input applied during a clock pulse, and permits a change of state only if the switching input is received by the flip-flop before the application of the clock pulse.
Inventors
- 👤 Ramachandra Aragula Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:31
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
199 words
A clocked flip-flop assembly, comprising a master flip-flop, a slave flip-flop, means responsive to the absence of a clock pulse for conducting the output of the master flip-flop to the slave flip-flop, a first AND-gate, a second AND-gate, a first clock pulse gate connected to the first and second AND-gates for providing enabling signals to the first and second AND-gates in response to the absence of a clock pulse, a second clock pulse gate responsive to the concurrance of a clock pulse and an output from either of the first and second AND-gates for providing an enabling signal to both the first and second AND-gates, whereby the absence of an output from the first and second AND-gates before the initiation of a clock pulse prevents the first and second AND-gates from producing an output during a clock pulse, a third AND-gate responsive to the concurrance of the presence of a clock pulse and an output from the first AND-gate for triggering the master flip-flop into a first state, and a fourth AND-gate responsive to the concurrance of the presence of a clock pulse and an output from the second AND-gate for triggering the master flip-flop into a second state.
Claim 2
Dependent Claim
199 words
A clocked flip-flop assembly, comprising a master flip-flop, a slave flip-flop, means responsive to the absence of a clock pulse for conducting the output of the master flip-flop to the slave flip-flop, a first AND-gate, a second AND-gate, a first clock pulse gate connected to the first and second AND-gates for providing enabling signals to the first and second AND-gates in response to the absence of a clock pulse, a second clock pulse gate responsive to the concurrance of a clock pulse and an output from either of the first and second AND-gates for providing an enabling signal to both the first and second AND-gates, whereby the absence of an output from the first and second AND-gates before the initiation of a clock pulse prevents the first and second AND-gates from producing an output during a clock pulse, a third AND-gate responsive to the concurrance of the presence of a clock pulse and an output from the first AND-gate for triggering the master flip-flop into a first state, and a fourth AND-gate responsive to the concurrance of the presence of a clock pulse and an output from the second AND-gate for triggering the master flip-flop into a second state.
Claim 3
Dependent Claim
143 words
A logic circuit for preventing a clocked flip-flop from being affected by a binary input signal initiated during a clock pulse period comprising a first gate means for providing a first enabling signal in response to the absence of a clock pulse, a second AND-gate means for conducting the binary input signal to an output terminal and to the clocked flip-flop in response to the concurrance of an enabling signal and the binary input signal, a third AND-gate means connected to the output of the second AND-gate means for providing a second enabling signal in response to the concurrance of a binary signal on the output terminal of the second AND-gate means and the presence of a clock pulse, and means for connecting the first and second enabling signals from the first and third gates to an input terminal of the second gate.
Claim 4
Dependent Claim
143 words
A logic circuit for preventing a clocked flip-flop from being affected by a binary input signal initiated during a clock pulse period comprising a first gate means for providing a first enabling signal in response to the absence of a clock pulse, a second AND-gate means for conducting the binary input signal to an output terminal and to the clocked flip-flop in response to the concurrance of an enabling signal and the binary input signal, a third AND-gate means connected to the output of the second AND-gate means for providing a second enabling signal in response to the concurrance of a binary signal on the output terminal of the second AND-gate means and the presence of a clock pulse, and means for connecting the first and second enabling signals from the first and third gates to an input terminal of the second gate.
Claim 5
Dependent Claim
516 words
A clocked flip-flop of the master slave type, comprising a first gate means having an input terminal, and a first and second output terminal for providing an enabling output on the first output terminal in response to the presence of a clock pulse and for providing an enabling signal on the second output terminal in response to the absence of a clock pulse, a second AND-gate means having an input terminal connected to the second output terminal of the first AND-gate means and having a second input terminal for the reception of a first binary input signal and a third input terminal for the reception of a first feedback signal, a third input AND-gate means having a first input terminal connected to the second output terminal of the first AND-gate means, a second input terminal for the reception of a second binary input signal and a third input terminal for the reception of a second feedback signal, a fourth AND-gate means having a first input terminal for the reception of clock pulses and a second input terminal connected to the output terminals of the second and third AND-gates for providing an enabling output on a first output terminal in response to the concurrance of a clock pulse and an output from either of the second and third AND-gates and for providing an enabling signal on a second output terminal in response to the absence of an output signal from both the second and third AND-gates or the absence of a clock pulse, whereby the second and third AND-gates are prevented from passing any bivalent input signals occurring after the reception of a clock pulse, the clocked flip-flop further comprising a master flip-flop, a fifth AND-gate having an input terminaL connected to the output terminal of the second AND-gate and to the first output terminal of the first AND-gate for passing the output of the second AND-gate to an input terminal of the master flip-flop in response to the enabling output on the first terminal of the first AND-gate, a sixth AND-gate having an input terminal connected to the output terminal of the third AND-gate and a second input terminal connected to the first output of the first AND-gate for passing the output of the third AND-gate to an additional terminal of the master flip-flop in response to the enabling output on the first output terminal of the first AND-gate, a slave flip-flop, means connected to the output of the master flip-flop and to the input of the slave flip-flop and further connected to the second output of the fourth AND-gate for passing the output of the master AND-gate to the slave AND-gate in response to an enabling system on the second output terminal of the fourth AND-gate, feedback means for connecting a first output terminal of the slave flip-flop to the third input terminal of the second AND-gate whereby the first feedback signal is provided for the second AND-gate, and means for connecting a complementary output of the slave flip-flop to the third input terminal of the third AND-gate whereby the second feedback signals are provided.
Claim 6
Dependent Claim
516 words
A clocked flip-flop of the master slave type, comprising a first gate means having an input terminal, and a first and second output terminal for providing an enabling output on the first output terminal in response to the presence of a clock pulse and for providing an enabling signal on the second output terminal in response to the absence of a clock pulse, a second AND-gate means having an input terminal connected to the second output terminal of the first AND-gate means and having a second input terminal for the reception of a first binary input signal and a third input terminal for the reception of a first feedback signal, a third input AND-gate means having a first input terminal connected to the second output terminal of the first AND-gate means, a second input terminal for the reception of a second binary input signal and a third input terminal for the reception of a second feedback signal, a fourth AND-gate means having a first input terminal for the reception of clock pulses and a second input terminal connected to the output terminals of the second and third AND-gates for providing an enabling output on a first output terminal in response to the concurrance of a clock pulse and an output from either of the second and third AND-gates and for providing an enabling signal on a second output terminal in response to the absence of an output signal from both the second and third AND-gates or the absence of a clock pulse, whereby the second and third AND-gates are prevented from passing any bivalent input signals occurring after the reception of a clock pulse, the clocked flip-flop further comprising a master flip-flop, a fifth AND-gate having an input terminaL connected to the output terminal of the second AND-gate and to the first output terminal of the first AND-gate for passing the output of the second AND-gate to an input terminal of the master flip-flop in response to the enabling output on the first terminal of the first AND-gate, a sixth AND-gate having an input terminal connected to the output terminal of the third AND-gate and a second input terminal connected to the first output of the first AND-gate for passing the output of the third AND-gate to an additional terminal of the master flip-flop in response to the enabling output on the first output terminal of the first AND-gate, a slave flip-flop, means connected to the output of the master flip-flop and to the input of the slave flip-flop and further connected to the second output of the fourth AND-gate for passing the output of the master AND-gate to the slave AND-gate in response to an enabling system on the second output terminal of the fourth AND-gate, feedback means for connecting a first output terminal of the slave flip-flop to the third input terminal of the second AND-gate whereby the first feedback signal is provided for the second AND-gate, and means for connecting a complementary output of the slave flip-flop to the third input terminal of the third AND-gate whereby the second feedback signals are provided.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |