System for the modification of data stored in recirculating delay lines

Claim 2

A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof; feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed; said logic matrix comprising a first section for the lowestorder memory stage and an additional section for each higherorder memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage.

Claim 3

A counting register as defined in claim 1 wherein each of said stages is provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.

Claim 4

A counting register as defined in claim 1 wherein said logic gates of each section include an OR gate provided with said single output connection and a plurality of AND gates connected in parallel to the input side of said OR gate.

Claim 5

A counting register as defined in claim 3 wherein said feedback means includes bistable means in each stage for delivering a direct output pulse Uk and a complementary output pulse Uk respectively representing the true value and the inverted value of a corresponding bit, said second set of leads including a respective conductor pair for each stage, the conductors of said pair being connnected to carry the pulses Uk and Uk, respectively, k being an integer identifying the respective stage.

Claim 6

A counting register as defined in claim 4 wherein the number of register stages is greater than two, said command means including switch means for selectively generating an adding command pulse Ca and its complement Ca on a first pair of leads of said first set, a subtracting command pulse Cs and its complement Cs on a second pair of leads of said first set, an entry command pulse Te and its complement Te on a third pair of leads of said first set, a unit command pulse T1 and its complement T1 on a fourth pair of leads of said first set, and a plurality of numerical pulses E1, E2 etc. on respective further leads of said first set, the number of said further leads equaling the number of said memory stages; the logic gates of said first stage comprising a first AND gate connected to receive the complementary first-stage output pulse U1 and the command pulses Ca and Te, a second AND gate connected to receive the complementary first-stage output pulse U1 and the command pulses Cs and Te, a third AND gate connected to receive the first numerical pulse E1 and the command pulse Te, a fourth AND gate connected to receive said unit command pulse T1, and a fifth AND gate connected to receive the first-stage output pulse U1 and the command pulses Ca, Cs, Te and T1; the logic gates of the second stage comprising a first EXCLUSIVE-OR gate connected to receive the direct output pulses U1 and U2 of said first and second stages, a second EXCLUSIVE-OR gate connected to receive the complementary first-stage output pulse U1 and the direct second-stage output pulse U2, a sixth AND gate connected to receive the output of said first EXCLUSIVE-OR gate and the command pulses Ca, Ta and T1, a seventh AND gate connected to receive the output of said second EXCLUSIVE-OR gate and the command pulses Cs, Te and T1, an eighth AND gate connected to receive the second numerical pulse E2 and the command pulses Te and T1, and a ninth AND gate connected to receive the direct second-stage output pulse U2 and the command pulses Ca, Cs, Te and T1; each further stage comprising a tenth AND gate connected to receive the direct output pulses of all preceding stages, an eleventh AND gate connected to receive the complementary output pulses of all preceding stages, a third EXCLUSIVE-OR gate connected to receive the output of said tenth AND gate and the direct output pulse of said further stage, a fourth EXCLUSIVE-OR gate connected to receive the output of said eleventh AND gate and the complementary output pulse of said further stage, a twelfth AND gate connected to receive the output of said third EXCLUSIVE-OR gate and the command pulses Ca, Te and T1, a thirteenth AND gate connected to receive the output of said fourth EXCLUSIVE-OR gate and the command pulses Cs, Te and T1, a fourteenth AND gate connected to receive the numerical pulse associated with said further stage and the command pulses Te and T1, and a fifteenth AND gate connected to receive the direct output pulse of said further stage and the command pulses Ca, Cs, Te and T1; each of said AND gates being further connected to another lead of said first set energized by said command means in the absence of a cancellation signal.

Claim 7

A counting register as defined in claim 4 wherein said command means includes switch means for selectively generating an incremental command pulse and the complement of said incremental command pulse on two leads of said first set, respectively, the logic gates of each stage including a first AND gate connected to one of said two leads for receiving said incremental command pulse and a second AND gate connected to the other of said two leads for receiving said complement thereof, said first AND gate of said first section being further connected to one of the conductors of the corresponding pair for receiving the complementary output pulse U1 of said first stage, said second AND gate of any section being further connected to the other conductor of said corresponding pair for receiving the direct output pulse Uk of the corresponding stage, said first AND gate of each additional section of said logic matrix having input connections to at least one of the paired conductors associated with the corresponding stage and with each lower-order stage.

Claim 8

A counting register as defined in claim 6 wherein said incremental command pulse is an adding pulse Ca having a complement Ca, said input connections of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function Uk + Zk where Zk is the logical product of the true values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal Ca and the complement Ca, respectively.

Claim 9

A counting register as defined in claim 6 wherein said incremental command pulse is a subtraction pulse Cs having a complement Cs, said input connectiOns of each additional section of said logic matrix including a logic network connected to supply to said first AND gate thereof the logical function Uk + Yk where Yk is the logical product of the inverted values of the respective bits of all preceding stages, said first and second AND gates of each additional section being connected to receive directly the command signal Cs and the complement Cs, respectively.

Claim 10

A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof; feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed; each of said stages being provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.

Claim 11

A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectively modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a delay line for the transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said delay line being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said delay line; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective delay line thereof; feedback means connecting the output of each stage with the input thereof through said logic matrix for periodically reinscribing each digital pulse on the same delay line to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected recurrence period, the information to be reinscribed; each of said stages being provided with an input flip-flop and an output flip-flop, a source of first and second clock pulses connected to said input flip-flop for respectively setting and resetting same in the presence of a control pulse in the output of said logic matrix, the input flip-flop being connected to energize said delay line in response to said first and second clock pulses for generating therein a digital pulse of a duration shorter than said recurrence period, differentiation means connected between said delay line and said output flip-flop for setting the latter in response to an edge of the delayed digital pulse, and a source of third clock pulses connected to said output flip-flop for resetting same, said first, second and third clock pulses having identical cadences corresponding to the reciprocal of said recurrence period.

Claim 12

A counting register as defined in claim 9 wherein said delay line is a magnetostrictive wire provided at one end with a writing coil connected to said input flip-flop and at the other end with a reading coil connected to said output flip-flop.

Claim 13

A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectIvely modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a magnetorestrictive wire provided at one end with a writing coil and at the other end with a reading coil for the delayed transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said wire between said coils being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said wire; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective wire thereof; feedback means connecting the reading coil of each stage with the writing coil thereof through said logic matrix for periodically reinscribing each digital pulse on the same wire to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected reCurrence period, the information to be reinscribed; said logic matrix comprising a first section for the lowest-order memory stage and an additional section for each higher-order memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of said logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage.

Claim 14

A counting register for concurrently storing a plurality of binary words conveying numerical information relating to a plurality of different items and for selectIvely modifying the information so stored, comprising: a plurality of substantially identical parallel memory stages including each a magnetorestrictive wire provided at one end with a writing coil and at the other end with a reading coil for the delayed transmission of a series of digital pulses from an input of each stage to an output thereof, each digital pulse representing a bit of a respective word, the delay time of said wire between said coils being a multiple of the fundamental recurrence period of said digital pulses whereby a plurality of such pulses can be simultaneously inscribed in said wire; a logic matrix connected to the inputs of all said stages for controlling the inscription of digital pulses on the respective wire thereof; feedback means connecting the reading coil of each stage with the writing coil thereof through said logic matrix for periodically reinscribing each digital pulse on the same wire to perpetuate the information stored in said register stages; and command means connected to said logic matrix for modifying, during a selected reCurrence period, the information to be reinscribed; said logic matrix comprising a first section for the lowest-order memory stage and an additional section for each higher-order memory stage, a first set of leads common to all said sections and selectively energizable by said command means, a second set of leads common to all said sections and selectively energizable by said feedback means, and a plurality of said logic gates in each section having input connections to respective combinations of leads from said first and second sets and having a single output connection to the input of the corresponding memory stage.