Patent US3603773A successfully refreshed from Google Patents.
US3603773A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital pulse rate generator
Assignee: Vernitron Corp
•
Filing: 1969-08-28
•
Granted: 1971-09-07
•
Expires: 1989-08-28
Abstract
Abstract In a variable pulse rate generator, a digital number is applied as parallel bits to a first bit register which stores and then transfers the bits to a bit adder under control of a clocked logic circuit. The bit adder applies its parallel bit output to a second bit register which feeds the bits back to the adder for accumulation. Periodically the adder applies a most significant bit to a pulse shaper thus creating a variable frequency output proportional to the value of the original digital number.
Inventors
- 👤 Joseph Caristein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03M; H03M1/00; H03M1/66; H03M1/86
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
193 words
An electronic computer system for generating a train of pulses whose frequency is proportional to a digital number, comprising a source of input strobe pulses a first register having a plurality of inputs and capable of storing a plurality of binarily weighted bits representing a digital number, said register responsive to an input strobe pulse from said source to change the number stored in said register; a multiple bit adder arranged to receive stored parallel bits from said first register; a second register adapted to store a plurality of binarily weighted bits and arranged to receive parallel bits from said multiple bit adder; a clock logic circuit for providing clock pulses and arranged to control said adder and to pass new parallel bits to said second register with each clock pulse; means for feeding a multiple bit output from said second register to said adder to add to bits received from said first register until said adder generates a carry output; and a pulse shaper arranged to receive said carry output from said adder to produce a pulse output at a variable frequency which is proportional to the magnitude of said digital number.
Claim 2
Dependent Claim
193 words
An electronic computer system for generating a train of pulses whose frequency is proportional to a digital number, comprising a source of input strobe pulses a first register having a plurality of inputs and capable of storing a plurality of binarily weighted bits representing a digital number, said register responsive to an input strobe pulse from said source to change the number stored in said register; a multiple bit adder arranged to receive stored parallel bits from said first register; a second register adapted to store a plurality of binarily weighted bits and arranged to receive parallel bits from said multiple bit adder; a clock logic circuit for providing clock pulses and arranged to control said adder and to pass new parallel bits to said second register with each clock pulse; means for feeding a multiple bit output from said second register to said adder to add to bits received from said first register until said adder generates a carry output; and a pulse shaper arranged to receive said carry output from said adder to produce a pulse output at a variable frequency which is proportional to the magnitude of said digital number.
Claim 3
Dependent Claim
80 words
An electronic computer system as defined in claim 1 further comprising means for inverting the input strobe pulse from said source and applying the inverted pulse to said clock logic circuit in inhibit action of said adder and said second register while a new digital number is being inserted into said first register and thereby prevent incorrect digital data from being processed in said adder and said second register whenever an input strobe pulse and a clock pulse are coincident.
Claim 4
Dependent Claim
81 words
An electronic computer system as defined in claim 2 further comprising delay circuit means interposed between said clock logic circuit and said second register to provide a time delay in each clock pulse arriving at said second register with respect to an undelayed clock pulse applied to said adder from said clock logic circuit, whereby new data is passed to said second register from said adder after the new data has had time to stabilize at the output of said adder.
Claim 5
Dependent Claim
107 words
An electronic computer system as defined in claim 3 further comprising a counter arranged to receive the variable frequency pulses from said pulse shaper; a digital-to-analog converter arranged to receive digital data from said counter; and a servosystem having a rotary output means, said servosystem being arranged to receive and respond to analog data from said converter, said analog data and said digital number both being representative of a desired rate of rotation of said rotary output means of said servosystem, whereby said rotary output means rotates at a variable rate depending on the magnitude of the digital number applied to and stored in said first register.
Claim 6
Dependent Claim
107 words
An electronic computer system as defined in claim 3 further comprising a counter arranged to receive the variable frequency pulses from said pulse shaper; a digital-to-synchro converter arranged to receive digital data from said counter; and a servosystem having a rotary output means, said servosystem being arranged to receive and respond to synchro data from said converter, said synchro data and said digital Number both being representative of a desired rate of rotation of said rotary output means of said servosystem, whereby said rotary output means rotates at a variable rate depending on the magnitude of the digital number applied to and stored in said first register.
Claim 7
Dependent Claim
107 words
An electronic computer system as defined in claim 3 further comprising a counter arranged to receive the variable frequency pulses from said pulse shaper; a digital-to-resolver converter arranged to receive digital data from said counter; and a servosystem having a rotary output means, said servosystem being arranged to receive and respond to resolver data from said converter, said resolver data and said digital number both being representative of a desired rate of rotation of said rotary output means of said servosystem, whereby said rotary output means rotates at a variable rate depending on the magnitude of the digital number applied to and stored in said first register.
Claim 8
Dependent Claim
132 words
An electronic computer system as defined in claim 3 further comprising a synchro-to-digital converter; a digital subtractor and scalor arranged to receive digital output data from said converter; a third register arranged to receive and store old digital output data from said converter while new digital output data is applied to said subtractor and scalor; means for applying the old digital data to said subtractor and scalor along with the new digital data from said converter to produce digital velocity data; means for applying said velocity data as parallel bits to said first register; and a counter and output register arranged to receive pulses of variable frequency from said pulse shaper whereby said counter and output register produce a digital output which precisely represents the digital output last computed by said converter.
Claim 9
Dependent Claim
132 words
An electronic computer system as defined in claim 3 further comprising, a resolver-to-digital converter; a digital subtractor and scalor arranged to receive digital output data from said converter; a third register arranged to receive and store old digital output data from said converter while new digital output data is applied to said subtractor and scalor; means for applying the old digital data to said subtractor and scalor along with the new digital data from said converter to produce digital velocity data; means for applying said velocity data as parallel bits to said first register; and a counter and output register arranged to receive pulses of variable frequency from said pulse shaper whereby said counter and output register produce a digital output which precisely represents the digital output last computed by said converter.
Claim 10
Dependent Claim
132 words
An electronic computer system as defined in claim 3 further comprising, a voltage-to-digital converter; a digital subtractor and scalor arranged to receive digital output data from said converter; a third register arranged to receive and store old digital output data from said converter while new digital output data is applied to said subtractor and scalor; means for applying the old digital data to said subtractor and scalor along with the new digital data from said converter to produce digital velocity data; means for applying said velocity data as parallel bits to said first register; and a counter and output register arranged to receive pulses of variable frequency from said pulse shaper whereby said counter and output register produce a digital output which precisely represents the digital output last computed by said converter.
References Cited (Backward Citations)
US2685054A
Cited
US3017098A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-06 | 1975-03-08 | 1975-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-06 | 1979-03-08 | 1979-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-06 | 1983-03-08 | 1983-09-07 | $7700.00 | Window Closed / Lapsed |