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US3602886A
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Self-checking error checker for parity coded data
Assignee: International Business Machines Corp
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Filing: 1968-07-25
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Granted: 1971-08-31
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Expires: 1988-07-25
Abstract
Abstract A series of self-checking error checking circuits are disclosed for checking conventional parity coded data lines. The data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. The circuit comprises at least 2 exclusive OR tree circuits wherein each tree obtains its inputs from different input lines whereby complementing outputs are produced by the two tree circuits for any correct signal set and wherein the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.
Inventors
- 👤 William C Carter
- 👤 Peter R Schneider
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
157 words
A self-testing error checking system for checking parity coded binary data appearing on a set of data lines, said data lines being divided into two distinct nonoverlapping groups, said checking circuit comprising two logic circuit means selectively connected to each group of data lines, each said logic circuit means performing the function of an Exclusive OR logic tree, and means for producing a single binary output from each of said logic circuit means, the two binary outputs from said two logic circuit means having a first predetermined data configuration when the parity coded binary data is correct and the checking circuit is producing no error and having a second predetermined data configuration when a single error is present in either the parity coded data or in the operation of the checking circuit and means connected to said outputs for sensing an error condition, said means possessing the characteristic of tolerating a single failure without producing an error.
Claim 2
Dependent Claim
157 words
A self-testing error checking system for checking parity coded binary data appearing on a set of data lines, said data lines being divided into two distinct nonoverlapping groups, said checking circuit comprising two logic circuit means selectively connected to each group of data lines, each said logic circuit means performing the function of an Exclusive OR logic tree, and means for producing a single binary output from each of said logic circuit means, the two binary outputs from said two logic circuit means having a first predetermined data configuration when the parity coded binary data is correct and the checking circuit is producing no error and having a second predetermined data configuration when a single error is present in either the parity coded data or in the operation of the checking circuit and means connected to said outputs for sensing an error condition, said means possessing the characteristic of tolerating a single failure without producing an error.
Claim 3
Dependent Claim
35 words
A self-testing error checking circuit as set forth in claim 1 wherein each of said logic circuit means comprises an Exclusive OR logic tree comprising a plurality of two input single output Exclusive OR circuits.
Claim 4
Dependent Claim
34 words
A self-testing error checker as set forth in claim 1 wherein each of said logic circuit means for testing n data lines of a particular group is composed of -1 individual Exclusive OR circuits.
Claim 5
Dependent Claim
66 words
A self-testing error checking circuit as set forth in claim 1 wherein the data is divided into two groups and two logic circuit means each including an Exclusive OR circuit tree are included in said checker wherein under error free conditions of the input data code and normal operation of the checker the outputs of the two logic circuit means are binary complements of each other.
Claim 6
Dependent Claim
55 words
A self-testing error checker as set forth in claim 4 wherein said input data is divided into two groups, each containing n and m bits wherein each of said logic circuit means includes n-1 and m-1 individual two input single output Exclusive OR circuits connected respectively to said n bit and m bit input groups.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |