Patent US3602828A successfully refreshed from Google Patents.
US3602828A
Expired / Lapsed
US
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Self-clocking detection system
Assignee: International Business Machines Corp
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Filing: 1969-10-27
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Granted: 1971-08-31
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Expires: 1989-10-27
Abstract
Abstract The invention relates to both a method and an apparatus for separating data and clock signals from a self-clocking encoded input signal by means of a self-clocking detector system which employs clock circuitry operating at the same frequency as the data rate embodied in the self-clocking encoded input signal.
Inventors
- 👤 Fred Kurzweil Jr
- 👤 Marco Padalino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:57
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
204 words
A binary data detection system comprising: an input signal having a rate of 2f, said input signal consisting of data pulses and clock pulses, said data pulses having a rate of f; a first means for generating a first and second signal each at a frequency of f, said first means comprising a ramp generator operating at a frequency of f; a second means receiving said input signal and said first and second signals from said first means for separating said data pulses from said clock pUlses of said input signal, said second means having a first output for data and a second output for clock; a third means for receiving the output of said ramp generator of said first means and said first and second output of said second means for generating an average error correction signal proportional to displacement of said data and clock pulses of said input signal from the center of the ramp output of said ramp generator; and said ramp generator of said first means receiving said average error correction signal from said third means causing the center of said ramp output of said ramp generator to correspond to the occurrence of said data pulses of said input signal.
Claim 2
Dependent Claim
204 words
A binary data detection system comprising: an input signal having a rate of 2f, said input signal consisting of data pulses and clock pulses, said data pulses having a rate of f; a first means for generating a first and second signal each at a frequency of f, said first means comprising a ramp generator operating at a frequency of f; a second means receiving said input signal and said first and second signals from said first means for separating said data pulses from said clock pUlses of said input signal, said second means having a first output for data and a second output for clock; a third means for receiving the output of said ramp generator of said first means and said first and second output of said second means for generating an average error correction signal proportional to displacement of said data and clock pulses of said input signal from the center of the ramp output of said ramp generator; and said ramp generator of said first means receiving said average error correction signal from said third means causing the center of said ramp output of said ramp generator to correspond to the occurrence of said data pulses of said input signal.
Claim 3
Dependent Claim
97 words
A binary data detection system as set forth in claim 1 wherein said second means comprises: a binary register for receiving said first and second signals from said first means and for generating a data window and a clock window; a first AND circuit for receiving said data window and said input signal, the output of said first AND circuit being said first output of said second means; and a second AND circuit for receiving said clock window and said input signal, the output of said second AND circuit being the second output of said second means.
Claim 4
Dependent Claim
112 words
A binary data detection system as set forth in claim 2 wherein said third means comprises: a delay for receiving the second output of said second means and for adjusting said second output of said second means to be in phase with said first output of said second means; an OR circuit for combining the first output of said second means with the output of said delay to create a third signal; and an error-generating means for comparing the occurrence of pulses in said third signal with the center of said ramp output of said ramp generator of said first means and for generating an average error correction signal from said comparison.
Claim 5
Dependent Claim
205 words
A binary data detection system as set forth in claim 3 wherein said first means comprises: a ramp generator operating at a frequency f and being responsive to said average error correction signal from said third means; a first pulse shaper for receiving the output of said ramp generator and for converging said ramp output of said ramp generator into a pulse train having a frequency of f; a one-half ramp generator synchronized to the output of said first pulse shaper and responsive to said average error correction signal of said third means; a second pulse shaper for receiving the ramp output of said one-half ramp generator and for converting said ramp output of said one-half ramp generator into a pulse train having a frequency of f; a first delay for receiving the output of said first pulse shaper and for adjusting the pulses of said pulse train from said first pulse shaper to correspond to the start of said data window of said second means; and a second delay for receiving output of said second pulse shaper and for adjusting the pulses of said pulse train from said second pulse shaper to correspond with the start of said clock window of said second means.
Claim 6
Dependent Claim
145 words
A binary data detection system as set forth in claim 3 wherein said first means comprises: a ramp generator operating at a frequency of f and said ramp generator being responsive to said average error correction signal from said third means; a pulse shaper for receiving the output of said ramp generator and for converting said output of said ramp generator into a pulse train having a frequency of f; a first delay for receiving the output of said pulse shaper and for adjusting the pulses of said pulse train from said pulse shaper to correspond with the start of said data window of said second means; and a second delay for receiving the output of said pulse shaper and for adjusting the pulses of said pulse train from said pulse shaper to correspond to the start of said clock window of said second means.
Claim 7
Dependent Claim
165 words
A binary data detection sYstem as set forth in claim 3 wherein said first means comprises: a ramp generator operating at a frequency of f and responsive to said average error correction signal from said third means; a first comparator for producing an output pulse whenever said output ramp of said ramp generator reaches a first reference level, the output of said comparator being said first signal of said first means and said first reference level on said ramp of said ramp generator corresponding in time to the start of said data window of said second means; and a second comparator for receiving the output from said ramp generator for generating an output pulse whenever the ramp of said ramp generator reaches a second reference level, the output of said second comparator being the second signal of said first means, said second reference level on said ramp of said ramp generator corresponding in time to the start of said clock window of said second means.
Claim 8
Independent Claim
193 words
A method for detecting data signals from an input signal encoded by a self-clocking code comprising the steps of: generating a ramp signal having the same frequency as the data rate of said data signals in said input signal; generating a first and second signal from said ramp signal, said first and said second signals both having the same frequency as said ramp signals; generating a data window signal and a clock window signal from said first and second signals; separating said data signal from said clock signals of said input signal by means of said data window signal and said clock window signal, placing said data signals on a first output line and said clock signals on a second output line; adjusting said clock signals on said second output line to be in phase with said data signals on said first output line; combining said adjusted clock signals with said data signals to form a controlled signal; generating an average error correction signal by comparing the phase relationship of said control signal with said ramp signal; controlling the frequency of said ramp signal as a function of said average error correction signal.
Claim 9
Independent Claim
193 words
A method for detecting data signals from an input signal encoded by a self-clocking code comprising the steps of: generating a ramp signal having the same frequency as the data rate of said data signals in said input signal; generating a first and second signal from said ramp signal, said first and said second signals both having the same frequency as said ramp signals; generating a data window signal and a clock window signal from said first and second signals; separating said data signal from said clock signals of said input signal by means of said data window signal and said clock window signal, placing said data signals on a first output line and said clock signals on a second output line; adjusting said clock signals on said second output line to be in phase with said data signals on said first output line; combining said adjusted clock signals with said data signals to form a controlled signal; generating an average error correction signal by comparing the phase relationship of said control signal with said ramp signal; controlling the frequency of said ramp signal as a function of said average error correction signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |