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US3601801A
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Parallel signal logic comparison circuit
Assignee: Safran Aircraft Engines SAS
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Filing: 1969-01-08
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Granted: 1971-08-24
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Expires: 1989-01-08
Abstract
Abstract A logic circuit to effect the comparison of a number m of lines in a set of n lines A and energized in any sequence with a number q of energized lines in a set of p lines B. A matrix has a series of n inputs linked to the n row lines and a series of p inputs linked to p column lines. At the nodes of the row and column lines, an AND gate is provided having an inverted output. The inverted output is connected to one input each of two AND gates each having another input supplied by the respective row or column line to provide an output from the row or column line at the nodal point if, and only if there is no coincidence of input. The row and column lines are connected to OR gates and to a comparator, energization of the row or column OR gate, respectively, indicating that the larger number of row or column lines was energized initially; if both OR gates are deenergized, the comparator will indicate equality of numbers of input lines energized.
Inventors
- 👤 Jacques Louis Sauvan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
259 words
Logic circuit to compare the number of energized lines m in a first set of n lines with the number of energized lines q in a second set of p lines in which the energization of specific lines in the sets is at random, and to obtain outputs indicative of: m<a; m q and m>q said circuit comprising a matrix having the sets of lines forming, respectively row and column inputs to the matrix; decoding circuits (3) arrangEd at the nodal junction points of the row and column lines of the matrix, each nodal junction comprising a first AND gate (4) having one input each connected to a row line and a column line leading to the nodal point, and having an inverted (I7) output; second and third AND gates (5, 6) one each associated with a row line (n) and a column line (p) respectively, each of said second and third AND gates having one input connected to the input side to the respective row or column line, and a second input connected to the inverted output from said first AND gate (4), to block outputs from the nodal points of row and column lines if there is coincidence of inputs to both row and column lines and to obtain output from the second and third AND gates (5, 6) only if there is noncoincidence of inputs to the row and column lines intersecting at the respective nodal point; and means (U21, 22) determining if there is any output from any row or column lines of the matrix.
Claim 2
Dependent Claim
259 words
Logic circuit to compare the number of energized lines m in a first set of n lines with the number of energized lines q in a second set of p lines in which the energization of specific lines in the sets is at random, and to obtain outputs indicative of: m<a; m q and m>q said circuit comprising a matrix having the sets of lines forming, respectively row and column inputs to the matrix; decoding circuits (3) arrangEd at the nodal junction points of the row and column lines of the matrix, each nodal junction comprising a first AND gate (4) having one input each connected to a row line and a column line leading to the nodal point, and having an inverted (I7) output; second and third AND gates (5, 6) one each associated with a row line (n) and a column line (p) respectively, each of said second and third AND gates having one input connected to the input side to the respective row or column line, and a second input connected to the inverted output from said first AND gate (4), to block outputs from the nodal points of row and column lines if there is coincidence of inputs to both row and column lines and to obtain output from the second and third AND gates (5, 6) only if there is noncoincidence of inputs to the row and column lines intersecting at the respective nodal point; and means (U21, 22) determining if there is any output from any row or column lines of the matrix.
Claim 3
Dependent Claim
75 words
Circuit according to claim 1, wherein the output detection means (U21, 22) comprises a pair of OR gates (21, 22) each having all its input connected to all the outputs of the respective row and column lines, output from either OR gate associated with the row, or column lines, respectively, indicating that a larger number of lines of the respective row or column lines of the set of lines (n, p) is energized (q>m; m>q).
Claim 4
Dependent Claim
69 words
Circuit according to claim 2, including an additional OR gate (U25) having its inputs connected to the outputs of both said OR gates (U21, U22), absence of output from said additional OR gate (U25) being indicative (I26) of no input from said pair of OR gates (21, 22) and hence of the quality of number of energized lines in both said sets of row and column lines (m q).
Claim 5
Dependent Claim
78 words
Circuit according to claim 1, wherein np(p2-p/2) decoding circuits are provided, in which n and p are, respectively, numbers of row and column lines, the matrix being divided by a diagonal (30) and all set decoding circuits are located at the nodal junction points of the row and column lines at one side of the diagonal, the remaining row and column nodal points not being interconnected, whereby a saving of (p2-p/2) decoding circuits in the matrix will result.
Claim 6
Dependent Claim
43 words
Circuit according to claim 4, wherein the diagonal line (30) starts at the matrix position p 1, n 1 and wherein the remaining decoding circuits are located at the side of the diagonal closest to the side of the n input row lines.
Claim 7
Dependent Claim
54 words
Circuit according to claim 1, including additional logic circuit means (42, 46; 50) connected to the lines of at least one 46, these sets and being connected to indicate when the input to a respective line in the set is energized but the output of the corresponding line is blocked by said decoding circuits.
Claim 8
Dependent Claim
98 words
Circuit according to claim 6, wherein the additional logic circuit decoding means comprises an additional AND gate (42) associated with selected ones of the row and column lines (40) each additional AND gate (42) having one input (43) connected to the input row, or column line, respectively of the matrix and a second input (44) connected to an inverted (I46) output from the respective row or column line, output being indicative of the specific row, or column line which is energized at the input to the matrix but of which the output from the matrix is not energized.
Claim 9
Dependent Claim
80 words
Circuit according to claim 6, wherein said additional logic circuit decoding means comprises an additional Or gate (50) associated with a respective row or column, each, having its inputs connected to the noninverted outputs of the first AND gates (4) of the decoding circuits in any one row, output from any OR gate being indicative of concurrent input of the row and column lines to a nodal point in the respective line with which the additional OR gate is associated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |