Abstract A pulse train regeneration system for regenerating a control pulse train, including at least two shift registers. Each of the shift registers is provided with at least a last stage, the last stage including flip-flops, an inverter, two coincidence circuits, each of the coincidence circuits being provided with at least two inputs, one input of each of the two inputs being connected to the output of a respective one of the shift registers, a train of the first of said two inputs timing pulse supplied to the input of the last stage and being supplied through the inverter to the first input of said two coincidence circuits timing pulse, the second timing pulse being time delayed with respect to the timing pulse train of the first inputs and being supplied to the other two inputs of the coincidence circuits, the control pulse train being supplied to the last stage and an output flip-flop having at least two inputs, each of the two inputs of the output flip-flop being connected to the output of a respective one of the two coincidence circuits.
A pulse train regeneration system for regenerating a control pulse train comprising two shift registers each of said two shift registers including at least a last stage, said last stage being provided with flip-flops, an inverter, two coincidence circuits, each of said two coincidence circuits being provided with at least two inputs, one input of each of said two inputs being connected to the outputs of a respective one of said shift registers, a timing pulse train of the first of said two inputs supplied to the input of said last stage and being supplied to the first inputs of said two coincidence circuits; a timing pulse train of the second inputs of said two inputs being time delayed with respect to said timing pulse train of the first inputs and being supplied through said inverter to the other inputs of the two coincidence circuits, said control pulse train being supplied to said last stage, and an output flip-flop having at least two inputs, each of said two inputs of said output flip-flop being connected to the output of a respective one of said two coincidence circuits.
Claim 2
Dependent Claim
187 words
A pulse train regeneration system for regenerating a control pulse train comprising two shift registers each of said two shift registers including at least a last stage, said last stage being provided with flip-flops, an inverter, two coincidence circuits, each of said two coincidence circuits being provided with at least two inputs, one input of each of said two inputs being connected to the outputs of a respective one of said shift registers, a timing pulse train of the first of said two inputs supplied to the input of said last stage and being supplied to the first inputs of said two coincidence circuits; a timing pulse train of the second inputs of said two inputs being time delayed with respect to said timing pulse train of the first inputs and being supplied through said inverter to the other inputs of the two coincidence circuits, said control pulse train being supplied to said last stage, and an output flip-flop having at least two inputs, each of said two inputs of said output flip-flop being connected to the output of a respective one of said two coincidence circuits.
Claim 3
Dependent Claim
21 words
A pulse train regeneration system as claimed in claim 1, wherein each of said two shift registers include a single flip-flop.
Claim 4
Dependent Claim
39 words
A pulse train regeneration system as claimed in claim 1, wherein the amount said second timing pulse is delayed with respect to said first timing pulse is at least one-half the time between repetition of said first timing pulse.