Patent US3601630A successfully refreshed from Google Patents.
US3601630A
Expired / Lapsed
US
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Mos circuit with bipolar emitter-follower output
Assignee: Texas Instruments Inc
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Filing: 1969-06-26
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Granted: 1971-08-24
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Expires: 1989-06-26
Abstract
Abstract An inverter for a metal-insulator-semiconductor integrated circuit which utilizes an MOS inverter stage followed by a bipolar emitter-follower stage is disclosed. The inverter stage may have multiple inputs to form a gate. The emitter-follower stage employs a bipolar transistor with an MOS transistor as the load impedance. The size of the output MOS transistor can be changed to provide optimum drive characteristics without redesigning the remainder of the integrated circuit. The emitterfollower output stage provides a very low output impedance, and therefore has the capability to drive higher capacitive loads.
Inventors
- 👤 Donald J Redwine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
43 words
In an integrated semiconductor logic circuit, a bipolar transistor and a first metal-insulator-semiconductor transistor connected in series between source and drain voltage supplies to form an emitter-follower output stage, and a logic control circuit connected to drive the base of the bipolar transistor.
Claim 2
Dependent Claim
43 words
In an integrated semiconductor logic circuit, a bipolar transistor and a first metal-insulator-semiconductor transistor connected in series between source and drain voltage supplies to form an emitter-follower output stage, and a logic control circuit connected to drive the base of the bipolar transistor.
Claim 3
Dependent Claim
68 words
The logic circuit defined in claim 1 wherein the logic circuit is an inverter stage comprising first and second metal-insulator-semiconductor transistors the channels of which are connected in series between source and drain voltage supplies, the gate of the first MOS transistor being the logic input of the inverter stage and the common drain-source being the logic output and being connected to the base of the bipolar transistor.
Claim 4
Dependent Claim
23 words
The logic circuit defined in claim 1 wherein the logic control circuit comprises a metal-insulator-semiconductor inverter stage having at least one logic input.
Claim 5
Dependent Claim
23 words
The logic circuit defined in claim 1 wherein the bipolar transistor is an NPN transistor and the metal-insulator-semiconductor transistor is a P-channel transistor.
Claim 6
Dependent Claim
23 words
The logic circuit defined in claim 1 wherein the bipolar transistor is a PNP transistor and the metal-insulator-semiconductor transistor is an N-channel transistor.
Claim 7
Dependent Claim
122 words
In an integrated MOS logic circuit, first and second MOS transistors the channels of which are connected in series between source and drain voltage supplies, the saturation impedance of the first MOS transistor being substantially smaller than the saturation impedance of the second MOS transistor, the gate of the first MOS transistor being the logic input, a bipolar transistor the collector-emitter circuit of which is connected in series with the channel of a third MOS transistor between the source and drain supply voltage, the base of the bipolar transistor being connected to the drain of the first MOS transistor and the emitter being the logic output, and the gates of the second and third transistors being connected to a gate supply voltage.
Claim 8
Dependent Claim
122 words
In an integrated MOS logic circuit, first and second MOS transistors the channels of which are connected in series between source and drain voltage supplies, the saturation impedance of the first MOS transistor being substantially smaller than the saturation impedance of the second MOS transistor, the gate of the first MOS transistor being the logic input, a bipolar transistor the collector-emitter circuit of which is connected in series with the channel of a third MOS transistor between the source and drain supply voltage, the base of the bipolar transistor being connected to the drain of the first MOS transistor and the emitter being the logic output, and the gates of the second and third transistors being connected to a gate supply voltage.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |