Patent US3601628A successfully refreshed from Google Patents.
US3601628A
Expired / Lapsed
US
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Precharge mos-bipolar output buffer
Assignee: Texas Instruments Inc
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Filing: 1969-06-25
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Granted: 1971-08-24
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Expires: 1989-06-25
Abstract
Abstract A two-phase, precharge MOS-bipolar output buffer for an integrated semiconductor circuit which utilizes a bipolar transistor and an MOS transistor formed on the same semiconductor chip and connected in push-pull configuration at the output. The bipolar transistor is turned ''''off'''' and the MOS transistor turned ''''on'''' regardless of the level of the logic input during a first pulsed clock to precharge the capacitive load to a logic ''''1,'''' then the bipolar transistor is kept ''''off'''' to maintain the logic ''''1'''' if the logic input is a logic ''''0'''' or is turned ''''on'''' to discharge the capacitive load if the input is a logic ''''1.'''' The output buffer can drive capacitive loads at high speed because the output MOS transistor can be made as large as necessary to charge the load rapidly without increasing the input capacitance and the gain of the bipolar device provides the necessary current to discharge the load rapidly.
Inventors
- 👤 Donald J Redwine
- 👤 Earl M Worstell Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:01
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6877; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/01855; H03K5/00; H03K5/01; H03K5/02; H03K5/023
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
96 words
The output buffer for an integrated semiconductor circuit comprising a bipolar transistor and an output field effect transistor connected in push-pull configuration with the emitter of said bipolar transistor being connected to the source of said field effect transistor, first circuit means for turning the bipolar transistor ''''off'''' during the pulses of a first clock voltage and for turning the output field effect transistor ''''on'''' to charge a load capacitance, and second circuit means for turning bipolar transistor ''''on'''' only in the absence of the clock pulse and the presence of a predetermined logic input signal.
Claim 2
Dependent Claim
96 words
The output buffer for an integrated semiconductor circuit comprising a bipolar transistor and an output field effect transistor connected in push-pull configuration with the emitter of said bipolar transistor being connected to the source of said field effect transistor, first circuit means for turning the bipolar transistor ''''off'''' during the pulses of a first clock voltage and for turning the output field effect transistor ''''on'''' to charge a load capacitance, and second circuit means for turning bipolar transistor ''''on'''' only in the absence of the clock pulse and the presence of a predetermined logic input signal.
Claim 3
Dependent Claim
85 words
The output buffer defined in claim 1 wherein the first circuit means comprises a second field effect transistor connecting the base of the bipolar transistor to a drain voltage supply, and the second circuit means comprises a third field effect transistor connecting the base of the bipolar transistor to the source voltage supply the gate of the third field effect transistor being the logic input, the saturation impedance of the third field effect transistor being substantially higher than that of the second field effect transistor.
Claim 4
Dependent Claim
65 words
The output buffer defined in claim 2 further characterized by a fourth field effect transistor connecting the emitter of the bipolar transistor to the drain supply voltage, the gate of the fourth field effect transistor being connected to a second pulsed clock voltage for turning the fourth field effect transistor ''''on'''' during a portion of the period when the first pulsed clock voltage is ''''off.''''
Claim 5
Dependent Claim
168 words
The integrated circuit comprising a substrate of one conductivity type, a plurality of diffused regions of the other conductivity type, at least one diffused region of said one conductivity type formed in one of the diffused regions of the other conductivity type to form a bipolar transistor, means forming a plurality of field effect channels between selected diffused regions of the other conductivity type to form field effect Transistors, and means forming an output buffer circuit comprising the bipolar transistor and a selected one of the field effect transistors connected in push-pull configuration, said one diffused region being connected to the diffused source region of the selected field effect transistor, first circuit means for turning the bipolar transistor ''''off'''' during the pulses of a first clock voltage and for turning said selected field effect transistor ''''on'''' to charge a load capacitance, and second circuit means for turning the bipolar transistor ''''on'''' only in the absence of the clock pulse and the presence of a predetermined logic input signal.
Claim 6
Dependent Claim
168 words
The integrated circuit comprising a substrate of one conductivity type, a plurality of diffused regions of the other conductivity type, at least one diffused region of said one conductivity type formed in one of the diffused regions of the other conductivity type to form a bipolar transistor, means forming a plurality of field effect channels between selected diffused regions of the other conductivity type to form field effect Transistors, and means forming an output buffer circuit comprising the bipolar transistor and a selected one of the field effect transistors connected in push-pull configuration, said one diffused region being connected to the diffused source region of the selected field effect transistor, first circuit means for turning the bipolar transistor ''''off'''' during the pulses of a first clock voltage and for turning said selected field effect transistor ''''on'''' to charge a load capacitance, and second circuit means for turning the bipolar transistor ''''on'''' only in the absence of the clock pulse and the presence of a predetermined logic input signal.
Claim 7
Dependent Claim
126 words
A precharge output buffer for an integrated semiconductor circuit comprising first and second MOS transistors connected in series between source ad drain voltage sources, the first MOS transistor having a substantially lower saturation impedance than the second MOS transistor, the gate of the second MOS transistor being the logic input, a third MOS transistor and a bipolar transistor connected in series between the source and drain voltage with the emitter of the bipolar transistor and the source of the third MOS transistor common and forming the logic output and with the base of said bipolar transistor connected to the common source-drain junction of said first and second MOS transistors, and a first pulsed clock voltage connected to the gates of the first and third MOS transistors.
Claim 8
Dependent Claim
126 words
A precharge output buffer for an integrated semiconductor circuit comprising first and second MOS transistors connected in series between source ad drain voltage sources, the first MOS transistor having a substantially lower saturation impedance than the second MOS transistor, the gate of the second MOS transistor being the logic input, a third MOS transistor and a bipolar transistor connected in series between the source and drain voltage with the emitter of the bipolar transistor and the source of the third MOS transistor common and forming the logic output and with the base of said bipolar transistor connected to the common source-drain junction of said first and second MOS transistors, and a first pulsed clock voltage connected to the gates of the first and third MOS transistors.
Claim 9
Dependent Claim
59 words
The precharge output buffer of claim 5 further comprising a fourth MOS transistor connected in parallel with the third MOS transistor, and a second pulsed clock voltage connected to the gate of the fourth MOS transistor for turning the fourth MOS transistor ''''on'''' during at least a portion of the period when the first pulsed clock voltage is ''''off.''''
References Cited (Backward Citations)
US3393325A
Cited
US3466511A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |