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US3601587A Expired / Lapsed US ⏱️ 0.0 years remaining

Register control system and method

Assignee: Hurletron Inc
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Filing: 1969-10-06
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Granted: 1971-08-24
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Expires: 1989-10-06
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Abstract

Abstract A digital control system for controlling register of a moving web at successive stations wherein the set point at each station is automatically obtained and stored while the web is running in the desired register condition.

Inventors

  • 👤 Paul W Thiede

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 23:35
CPC Classifications
B; B65; B65H; B65H23/00; B65H23/04; B65H23/18; B65H23/188; B65H23/1882

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 164 words
The method of setting up a digital register control system which includes a main counter having a memory register for determining the counting action thereof and an inspection zone counter set to provide a predetermined count prior to emitting a set point signal, which method comprises initiating a counting sequence in response to the occurrence of one of a reference signal and a scanner signal interposing in the counting sequence a delaying counter set to provide a count corresponding to the predetermined count of said inspection zone counter and delaying the counting sequence of the main counter until after completion of the counting cycle by the delaying counter, and sensing the occurrence of the other of the reference signal and scanner signal during the counting sequence and storing in the memory register the count of the main counter at the time of occurrence of such other signal, for use in controlling subsequent operation of the main counter in the absence of such delaying counter.
Claim 2
Independent Claim 164 words
The method of setting up a digital register control system which includes a main counter having a memory register for determining the counting action thereof and an inspection zone counter set to provide a predetermined count prior to emitting a set point signal, which method comprises initiating a counting sequence in response to the occurrence of one of a reference signal and a scanner signal interposing in the counting sequence a delaying counter set to provide a count corresponding to the predetermined count of said inspection zone counter and delaying the counting sequence of the main counter until after completion of the counting cycle by the delaying counter, and sensing the occurrence of the other of the reference signal and scanner signal during the counting sequence and storing in the memory register the count of the main counter at the time of occurrence of such other signal, for use in controlling subsequent operation of the main counter in the absence of such delaying counter.
Claim 3
Dependent Claim 304 words
In apparatus for providing a set point signal for use in sensing register errors with respect to a moving web, means for generating encoder pulses as a function of web movement and for generating a cyclically occurring reference signal to initiate successive error-sensing cycles, scanner means for generating a scanner signal whose time of occurrence is responsive to register errors relative to said reference signal in each error-sensing cycle, and counting means including a main counter with a memory register for storing a count value controlling the count at which the main counter supplies an output signal, said counting means being operable to count encoder pulses beginning with the occurrence of one of said reference signals and to emit a set point signal which is to be time coincident with one of said scanner signals, wherein the improvement compriseS setup circuitry for operation in a setup cycle while the web has substantially a zero registration error to cause counting of encoder pulses beginning with the occurrence of a reference signal and ending with the occurrence of a scanner signal to provide an encoder count equal to the correct spacing between the reference signal and the scanner signal, and means operable during the setup cycle only for delaying the counting of encoder pulses be the main counter for a time interval corresponding to the time spacing between the occurrence of the output signal from the main counter and the set point signal in normal operation, thereby to produce a count in the main counter of the correct value for normal operation, said memory register of said main counter being automatically operable to store said count of the main counter during the setup cycle and thereafter to control the main counter in accordance with such count during normal operation where the delaying time interval is omitted.
Claim 4
Dependent Claim 304 words
In apparatus for providing a set point signal for use in sensing register errors with respect to a moving web, means for generating encoder pulses as a function of web movement and for generating a cyclically occurring reference signal to initiate successive error-sensing cycles, scanner means for generating a scanner signal whose time of occurrence is responsive to register errors relative to said reference signal in each error-sensing cycle, and counting means including a main counter with a memory register for storing a count value controlling the count at which the main counter supplies an output signal, said counting means being operable to count encoder pulses beginning with the occurrence of one of said reference signals and to emit a set point signal which is to be time coincident with one of said scanner signals, wherein the improvement compriseS setup circuitry for operation in a setup cycle while the web has substantially a zero registration error to cause counting of encoder pulses beginning with the occurrence of a reference signal and ending with the occurrence of a scanner signal to provide an encoder count equal to the correct spacing between the reference signal and the scanner signal, and means operable during the setup cycle only for delaying the counting of encoder pulses be the main counter for a time interval corresponding to the time spacing between the occurrence of the output signal from the main counter and the set point signal in normal operation, thereby to produce a count in the main counter of the correct value for normal operation, said memory register of said main counter being automatically operable to store said count of the main counter during the setup cycle and thereafter to control the main counter in accordance with such count during normal operation where the delaying time interval is omitted.
Claim 5
Dependent Claim 63 words
Apparatus according to claim 2 with said setup circuitry having a memory-set switch for selective actuation to initiate a setup during which a new count value is automatically stored in said memory register as a function of a scanner signal occurring after actuation of the memory-set switch is completed, whereby a different scanner signal may be selected from which to determine register errors.
Claim 6
Dependent Claim 43 words
Apparatus according to claim 2 wherein a mark discriminator switch is connected with said setup circuitry but is physically located adjacent said scanner means, said switch being actuatable to initiate a setup cycle with respect to a visually observed mark on the web.

References Cited (Backward Citations)

US2980858A Cited
US3068787A Cited
US3454926A Cited
US3440547A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-08-23 1975-02-22 1975-08-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-08-23 1979-02-22 1979-08-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-08-23 1983-02-22 1983-08-24 $7700.00 Window Closed / Lapsed

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