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US3601546A
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Selection of a time multiplex shared register and use of a common data buffer in a communication switching system
Assignee: GTE Automatic Electric Laboratories Inc
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Filing: 1970-02-02
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Granted: 1971-08-24
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Expires: 1990-02-02
Abstract
Abstract Each register-sender is assigned an individual junctor, an area of memory, and a recurring time slot of a multiplex cycle; and each during its time slot has use of common process control logic circuits which include a sequence state register. The registersender subsystem includes a data buffer for communication with a marker. Upon origination of a call the marker sends a call-forservice signal to a seizure gate of the data buffer. Another input of the seizure gate is the idle state output of the sequence state register, so that when the time slot of an idle register-sender occurs, the output of the gate sets a ''''key-tomarker'''' flip-flop and a ''''busy'''' flip-flop. This enables call data to be received from the marker and the sequence state to be advanced for that register-sender. The ''''key-to-marker'''' flipflop is reset at the end of the time slot, and again set during each occurrence thereof, while the ''''busy'''' flip-flop remains set, until the data reception is finished. A register-sender may also initiate seizure of the data buffer via the process control sequence state register during a call to send data to the marker. A ''''conditional busy'''' flip-flop permits queueing of one register-sender for use of the data buffer.
Inventors
- 👤 David K K Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:31
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
339 words
In a communication switching system comprising a plurality of register junctors, processing circuits common to the register junctors, a memory having a plurality of storage elements organized into sets which are individually associated with the register junctors; sequential addressing means providing cyclically recurring time slots individual to the register junctors and associated sets of the memory; means including the address means for causing the processing circuits to receive information from each register junctor and the associated set of the memory, to process the information and to write the information into said set, during each occurrence of the corresponding time slot; each said set of the memory including a subset for storing a state-indicating digit having a plurality of possible values, one of which is An idle-indicating value, said processing circuits including a state-indicating store 3 connected to receive and store state-indicating information from said subset of each set during the corresponding time slot, said store having an idle-state output DCX1 for indicating when said idleindicating value is true, a data buffer unit 900 having means for receiving originating call information for storage in the memory; the improvement wherein said data buffer unit includes a ''''key'''' bistable device KM, a call request lead MCFS seizure means 802 coupled to the call request lead, to said idle-state output from said store, and to an input of said device; the seizure means being operative responsive to coincidence of a call request signal on said lead and a signal indicating the idle value on said idle-state output to produce a seizure signal which is effective to set said bistable device, and means 501, 530, 111 in the processing circuits responsive to said ''''key'''' bistable device being set to change the value of the state-indicating digit in the set of the memory corresponding to the current time slot to an ''''originating seized'''' state DCX2; whereby a call request signal causes scanning of the register junctors by checking the value of the state-indicating digit during each time slot to find and seize an idle one.
Claim 2
Dependent Claim
339 words
In a communication switching system comprising a plurality of register junctors, processing circuits common to the register junctors, a memory having a plurality of storage elements organized into sets which are individually associated with the register junctors; sequential addressing means providing cyclically recurring time slots individual to the register junctors and associated sets of the memory; means including the address means for causing the processing circuits to receive information from each register junctor and the associated set of the memory, to process the information and to write the information into said set, during each occurrence of the corresponding time slot; each said set of the memory including a subset for storing a state-indicating digit having a plurality of possible values, one of which is An idle-indicating value, said processing circuits including a state-indicating store 3 connected to receive and store state-indicating information from said subset of each set during the corresponding time slot, said store having an idle-state output DCX1 for indicating when said idleindicating value is true, a data buffer unit 900 having means for receiving originating call information for storage in the memory; the improvement wherein said data buffer unit includes a ''''key'''' bistable device KM, a call request lead MCFS seizure means 802 coupled to the call request lead, to said idle-state output from said store, and to an input of said device; the seizure means being operative responsive to coincidence of a call request signal on said lead and a signal indicating the idle value on said idle-state output to produce a seizure signal which is effective to set said bistable device, and means 501, 530, 111 in the processing circuits responsive to said ''''key'''' bistable device being set to change the value of the state-indicating digit in the set of the memory corresponding to the current time slot to an ''''originating seized'''' state DCX2; whereby a call request signal causes scanning of the register junctors by checking the value of the state-indicating digit during each time slot to find and seize an idle one.
Claim 3
Dependent Claim
269 words
In a communication switching system, the combination as claimed in claim 1, wherein the system includes a switching network and marker, with the marker coupled to said data buffer unit via a data bus comprising a plurality of conductors, one of the conductors being said call request lead; wherein said data buffer unit is operative following said seizure signal to receive originating call information from the marker, and to return information including the identity of the register junctor corresponding to the time slot occurring at the time of seizure, for use by the marker to establish a connection through the switching network to that register junctor; wherein the data buffer unit further includes a ''''busy'''' bistable device and means to set it responsive to said seizure signal, means to reset the ''''key'''' bistable device before the end of the time slot, and means to set it again responsive to an ''''originating seized'''' state signal from said state-indicating store near the beginning of the next occurrence of the time slot of the seized register junctor to identify which junctor is using the data buffer unit, while the ''''busy'''' bistable device remains continuously set to prevent use of the data buffer unit for other calls by inhibiting said seizure means; means for the data buffer unit to receive a data message from the marker after the connection through the switching network to the register junctor has been completed, and means responsive to receipt of the message to cause the value of the state-indicating digit to be advanced, and means to clear the data buffer unit including resetting the ''''busy'''' bistable device.
Claim 4
Dependent Claim
233 words
In a communication switching system, the combination as claimed in claim 2, wherein the call processing circuits include means effective during the processing of a call to set the value of the state-indicating digit to a ''''request-marker'''' state, wherein the data buffer unit further a ''''common call'''' bistable device CF having an output connected to a common call request lead of the data bus to the marker, gate means having an input from the ''''request-marker'''' state output from said state-indicating store, and an inhibit input from the ''''busy'''' bistable device, operative responsive to the ''''request-marker'''' signal and the data buffer unit being idle to set the ''''Key,'''' the ''''busy,'''', and the ''''common call'''' bistable devices; means to load call information from the memory into the data buffer unit and to send it to the marker for use to establish a connection through the switching network; means in the prOcessing circuits responsive to the ''''key'''' bistable device being set to change the value of the state-indicating digit to a ''''marker-making-connection'''' state, means responsive to that state signal from the state-indicating store to set the ''''key'''' bistable device at the beginning of each occurrence of the same time slot, it being reset at the end of the time slot; and means to receive a data message which causes the value of the state-indicating digit to be advanced, and the data buffer unit to be cleared.
Claim 5
Dependent Claim
111 words
In a communication switching system, the combination as claimed in claim 3, wherein the data buffer unit further includes a ''''conditional busy'''' bistable device, means responsive to said ''''request-marker'''' state signal and the ''''key'''' bistable device not being set to set the ''''conditional busy'''' device and to change the value of the state-indicating digit to a ''''waiting'''' state, means in the data buffer responsive to the ''''conditional busy'''' device being set to inhibit seizure in response to ''''request marker'''' signals, and means responsive to coincidence of the ''''waiting'''' state signal and the ''''busy'''' device being reset to seize the data buffer unit be setting the ''''Key,'''' ''''busy'''' and ''''common call'''' devices.
Claim 6
Dependent Claim
51 words
In a communication switching system, the combination as claimed in claim 4, wherein there are a plurality of types of connections for which a marker request may be initiated from the processing circuits, and for each type there are separate values of the state-indicating digit for ''''request marker,'''' ''''marker-making-connection,'''' and ''''waiting.''''
References Cited (Backward Citations)
US3328534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |