Time division multiplex communication system

Claim 2

A time division multiplex communication system having a plurality of stations, each of at least one of said stations having a transmitter arrangement for transmitting the information signals at the respective channel positions preliminarily allotted thereto in at least one burst, said burst being located in each time division frame in a variably prescribed manner and thus variable in the sum width, each of at least one of said stations having a receiver arrangement for receiving the information signals placed at least at one of said channel positions, wherein the improvement comprises in said transmitter arrangement: first means responsive to the demand of transferring the transmission of the information signals from a first channel position in the burst to that second channel position in the burst which is presently idle, for temporarily causing said transmitter arrangement to transmit the last-mentioned information signals in duplicate at said first and said second channel positions and second means for causing, at a time posterior to the appearance of the last-mentioned signals in duplicate, said transmitter arrangement to discontinue the transmission of the lastmentioned signals at said first channel position only, thereby varying said sum width in compliance with said demand.

Claim 3

A transmitter arrangement in a station of a time division multiplex communication system, for transmitting the information signals at the respective channel positions preliminarily allotted thereto in at least one burst, said burst being located in each time division frame in a variably prescribed manner and thus variable in the sum width, another station of said system having a receiver arrangement for receiving the information signals of the optional at least one of said channels, wherein the improvement comprises: first means responsive to the demand of transferring the transmission of the information signals from a first channel position in the burst to that second channel position in the burst which is presently idle, for temporarily causing said transmitter arrangement to transmit the last-mentioned information signals in duplicate at said first and said second channel positions and second means for causing, at a time posterior to the appearance of the last-mentioned signals in duplicate, said transmitter arrangement to discontinue the transmission of the last-mentioned signals at said first channel position only, thereby varying said sum width in compliance with said demand.

Claim 4

A transmitter arrangement in a station of a time division multiplex communication system, for transmitting the information signals at the respective channel positions preliminarily allotted thereto in at least one burst, said burst being located in each time division frame in a variably prescribed manner and thus variable in the sum width, another station of said system having a receiver arrangement for receiving the information signals of the optional at least one of said channels, wherein the improvement comprises: first means responsive to the demand of transferring the transmission of the information signals from a first channel position in the burst to that second channel position in the burst which is presently idle, for temporarily causing said transmitter arrangement to transmit the last-mentioned information signals in duplicate at said first and said second channel positions and second means for causing, at a time posterior to the appearance of the last-mentioned signals in duplicate, said transmitter arrangement to discontinue the transmission of the last-mentioned signals at said first channel position only, thereby varying said sum width in compliance with said demand.

Claim 5

A receiver arrangement in a station of a time division multiplex communication system having a transmitter arrangement in another station, said transmitter arrangement having means responsive to the demand of transferring the transmission of the information signals from a first channel position in a burst to a second channel position in the burst, said second channel position being presently idle, for temporarily causing said transmitter arrangement to transmit said information signals in duplicate at said first and said second channel positions and for causing, at a time posterior to the appearance of said information signals in duplicate, said transmitter arrangement to discontinue the transmission of said information signals at said first channel position, wherein the improvement comprises: means responsive to the information signals sent in said duplicate fashion for deriving the information carried by said sigNals from one of said first and said second channel positions.

Claim 6

A receiver arrangement in a station of a time division multiplex communication system having a transmitter arrangement in another station, said transmitter arrangement having means responsive to the demand of transferring the transmission of the information signals from a first channel position in a burst to a second channel position in the burst, said second channel position being presently idle, for temporarily causing said transmitter arrangement to transmit said information signals in duplicate at said first and said second channel positions and for causing, at a time posterior to the appearance of said information signals in duplicate, said transmitter arrangement to discontinue the transmission of said information signals at said first channel position, wherein the improvement comprises: means responsive to the information signals sent in said duplicate fashion for deriving the information carried by said sigNals from one of said first and said second channel positions.

Claim 7

A time division multiplex signaling system, comprising in combination: a transmitting terminal including: a source of input information signals; a multiplexer for converting said input information signals into time division multiplexed signals; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst and producing a signal for synchronizing said burst; carrier means for transmitting said predetermined signals; a memory channel specifier including a plurality of channel units; a first program-controlled processor for producing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store said preassigned first channel position signal; said processor also transmitting in said transmitted carrier signals a signal representing said signal burst as identifying said transmitting terminal, a signal representing said preassigned first channel position in said burst and a signal representing said identifier preselected channel unit; a first timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; and a generator having signal comparators corresponding to said specifier channel units for comparing said preassigned first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals as corresponding to said preassigned first channel position signal; a receiving terminal including: a receiver for said carrier-transmitted predetermined signals; means for demodulating said received carrier signal to provide reproductions of said predetermined signals, said burst-synchronizing signal, and said burst, said preassigned first channel position and said preselected channel unit signals; means for decoding saId reproduced predetermined signals to provide decoded multiplexed information signals; means for demultiplexing said decoded multiplexed signals to provide a distribution of replicas of said input information signals as derived from said preassigned first channel position in said burst; a second program-controlled processor responsive to said reproduced burst, preassigned first channel position, and said preselected channel unit signals for producing a signal representing said burst-identifying signal, a signal representing said preassigned first channel position in said burst and signal representing said preselected channel unit in said transmitting terminal specifier; a memory burst and channel identifier having channel units corresponding to said transmitting terminal specifier channel units for storing said burst and first channel position signals in such one of said identifier channel units as is preselected by said second processor preselected channel unit signal; a second timing circuit responsive to said reproduced burst-synchronizing signal for deriving a burst-timing signal and a first channel position signal corresponding to said transmitting terminal burst and preassigned first channel position signals, respectively; and a generator having signal comparators corresponding to said identifier channel units for comparing said burst and first channel position signals stored in said preselected identifier channel unit with said second timing circuit derived burst and first channel position signals, respectively, for producing upon coincidence between said last-mentioned respective corresponding sIgnals a resampling signal to activate said demultiplexing means to distribute said replicas of said input information signals as derived from said reproduced predetermined signals placed in said first channel position in said burst; and means for transmitting said input information signals as said predetermined signals in a preassigned second channel position in said burst at said transmitting terminal and distributing said information signal replicas from said last-mentioned position at said receiving terminal, comprising: said transmitting terminal including: said first processor responsive to a demand signal for changing channel positions as arising in said transmitting terminal to transmit said input information signals in a second channel position in said burst thereby being caused to produce a further first channel position signal, a signal representing said second channel position and a signal corresponding to said specifier preselected channel unit; said first processor transmitting said burst, said further first channel position, said second channel position, and said corresponding channel unit signals in said carrier signals; means responsive to said further first channel position and said second channel position signals to derive a portion from said predetermined signals for placement in said first channel position in said burst at the time of said first channel position signal; said last-mentioned means further responsive to said corresponding channel unit signal applied to said specifier as stimulated by a predetermined timing signal originating in said first timing circuit to activate said sampling generator to produce a sampling signal to place said predetermined signal portion in a second channel position in said burst; said receiving terminal including: said second processor responsive to said reproduced burst-identifying signal, said further first channel position signal, said second channel position signal and said corresponding channel unit signal as demodulated form said received carrier signals including said predetermined signal portion in said second channel position in said burst for further producing a signal corresponding to said burst signal, a signal corresponding to said second channel position, and a signal representing said transmitting terminal preselected channel unit; and means responsive to said second processor produced corresponding burst, second channel position and preselected channel unit signals together with a predetermined timing signal derived from said demodulated burst-synchronizing signal in said second timing circuit to activate said identifier to produce a signal to energize said resampling generator to produce another resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said reproduced predetermined signal portion placed in said second channel position in said burst.

Claim 8

A time division multiplex signaling system, comprising in combination: a transmitting terminal including: a source of input information signals; a multiplexer for converting said input information signals into time division multiplexed signals; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst and producing a signal for synchronizing said burst; carrier means for transmitting said predetermined signals; a memory channel specifier including a plurality of channel units; a first program-controlled processor for producing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store said preassigned first channel position signal; said processor also transmitting in said transmitted carrier signals a signal representing said signal burst as identifying said transmitting terminal, a signal representing said preassigned first channel position in said burst and a signal representing said identifier preselected channel unit; a first timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; and a generator having signal comparators corresponding to said specifier channel units for comparing said preassigned first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals as corresponding to said preassigned first channel position signal; a receiving terminal including: a receiver for said carrier-transmitted predetermined signals; means for demodulating said received carrier signal to provide reproductions of said predetermined signals, said burst-synchronizing signal, and said burst, said preassigned first channel position and said preselected channel unit signals; means for decoding saId reproduced predetermined signals to provide decoded multiplexed information signals; means for demultiplexing said decoded multiplexed signals to provide a distribution of replicas of said input information signals as derived from said preassigned first channel position in said burst; a second program-controlled processor responsive to said reproduced burst, preassigned first channel position, and said preselected channel unit signals for producing a signal representing said burst-identifying signal, a signal representing said preassigned first channel position in said burst and signal representing said preselected channel unit in said transmitting terminal specifier; a memory burst and channel identifier having channel units corresponding to said transmitting terminal specifier channel units for storing said burst and first channel position signals in such one of said identifier channel units as is preselected by said second processor preselected channel unit signal; a second timing circuit responsive to said reproduced burst-synchronizing signal for deriving a burst-timing signal and a first channel position signal corresponding to said transmitting terminal burst and preassigned first channel position signals, respectively; and a generator having signal comparators corresponding to said identifier channel units for comparing said burst and first channel position signals stored in said preselected identifier channel unit with said second timing circuit derived burst and first channel position signals, respectively, for producing upon coincidence between said last-mentioned respective corresponding sIgnals a resampling signal to activate said demultiplexing means to distribute said replicas of said input information signals as derived from said reproduced predetermined signals placed in said first channel position in said burst; and means for transmitting said input information signals as said predetermined signals in a preassigned second channel position in said burst at said transmitting terminal and distributing said information signal replicas from said last-mentioned position at said receiving terminal, comprising: said transmitting terminal including: said first processor responsive to a demand signal for changing channel positions as arising in said transmitting terminal to transmit said input information signals in a second channel position in said burst thereby being caused to produce a further first channel position signal, a signal representing said second channel position and a signal corresponding to said specifier preselected channel unit; said first processor transmitting said burst, said further first channel position, said second channel position, and said corresponding channel unit signals in said carrier signals; means responsive to said further first channel position and said second channel position signals to derive a portion from said predetermined signals for placement in said first channel position in said burst at the time of said first channel position signal; said last-mentioned means further responsive to said corresponding channel unit signal applied to said specifier as stimulated by a predetermined timing signal originating in said first timing circuit to activate said sampling generator to produce a sampling signal to place said predetermined signal portion in a second channel position in said burst; said receiving terminal including: said second processor responsive to said reproduced burst-identifying signal, said further first channel position signal, said second channel position signal and said corresponding channel unit signal as demodulated form said received carrier signals including said predetermined signal portion in said second channel position in said burst for further producing a signal corresponding to said burst signal, a signal corresponding to said second channel position, and a signal representing said transmitting terminal preselected channel unit; and means responsive to said second processor produced corresponding burst, second channel position and preselected channel unit signals together with a predetermined timing signal derived from said demodulated burst-synchronizing signal in said second timing circuit to activate said identifier to produce a signal to energize said resampling generator to produce another resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said reproduced predetermined signal portion placed in said second channel position in said burst.

Claim 9

The system according to claim 4 in which said transmitting terminal predetermined signal portion deriving means includes a first channel position memory circuit for storing said further first channel position signal and a second channel position memory means for storing said second channel position signal and said signal corresponding to said specifier preselected channel unit.

Claim 10

The system according to claim 5 in which said transmitting terminal signal portion deriving means includes first and second channel position specifier memory circuits for comparing said further first and second channel position signals stored in said first and second channel position memory circuits, respectively, with said first timing circuit one channel position signal and a second channel position signal provided by said first timing circuit to produce output first and second channel position timing signals, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals.

Claim 11

The system according to claim 6 in which said transmitting Terminal predetermined signal portion deriving means includes a predetermined signal memory circuit responsive to preassigned clock pulses, said first and second channel specifier memory circuit output first and second channel position timing signals and said predetermined signals for providing said first predetermined signal portion to be placed in said second channel position in said burst.

Claim 12

The system according to claim 7 in which said predetermined signal memory circuit includes: an OR gate receiving said first and second channel specifier memory circuit output first and second channel position timing signals; a clock AND gate receiving said clock pulses and an output of said OR gate for producing stepping pulses lasting an eight-bit interval; a writing AND gate receiving said predetermined signals placed in said first channel position in said burst and said second channel position specifier memory circuit output timing signal for deriving a portion of said predetermined signals to be placed in said second channel position in said burst; an eight-stage shift register receiving said derived predetermined signal portion and said eight-bit interval clock pulses for storing said derived predetermined signals portion; and a reading AND gate receiving the output of said shift register and said first channel position specifier memory circuit output signal for reading out said predetermined signal portion stored in said shift register.

Claim 13

The system according to claim 7 in which said transmitting terminal predetermined signal portion deriving means includes a rewriting circuit activated by a rewriting pulse predetermined in time as produced in said first timing circuit to transfer said corresponding preselected channel unit signal from said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said sampling generator to provide a sampling signal to cause said multiplexing means to place said predetermined signals portion as provided by said predetermined signal memory circuit in said second channel position in said burst.

Claim 14

The system according to claim 4 in which said transmitting terminal predetermined signal portion deriving means comprises: a first channel position memory circuit for storing said further first channel position signal and a second channel position memory circuit for storing said second channel position signal and said signal corresponding to said specifier preselected channel unit; first and second channel position specifier memory circuits for comparing said further first and second channel position signals as stored in said respective first and second channel position memory circuits with said first timing circuit one channel position signal and a second channel position signal provided by said first timing circuit to produce output first and second channel position timing signals, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals; a predetermined signal memory circuit responsive to preassigned clock pulses, said first and second channel specifier memory circuit output first and second channel position timing signals and said predetermined signals in the output of said encoding means for providing said predetermined signal portion; and a rewriting circuit activated by a rewriting pulse predetermined in time as produced in said first timing circuit to transfer said corresponding preselected channel unit signal from said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said sampling generator to provide a sampling signal to cause said multiplexing means to place said predetermined signal position in said second channel position in said burst.

Claim 15

The system according to claim 4 in which said receiving terminal means responsive to said second processor burst, second channel poSition and preselected channel unit signals comprises a transfer memory circuit for storing said last-mentioned burst, second channel position and preselected channel unit signals.

Claim 16

The system according to claim 11 in which said receiving terminal means responsive to said second processor burst, second channel position and preselected channel unit signals, comprises: rewriting pulse producing means for decoding said demodulated burst-synchronizing signal to provide a rewriting pulse representing said second channel position in said burst; and a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and preselected channel unit signals from said transfer memory circuit to activate said identifier to produce a signal to energize said resampling generator to produce said another resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said predetermined signal portion placed in said second channel position in said burst.

Claim 17

The system according to claim 4 in which said receiving terminal means responsive to said second processor burst, second channel position and preselected channel unit signals, comprises: a transfer memory circuit for storing said last-mentioned burst, second channel position and preselected channel unit signals; rewriting pulse-producing means for decoding said demodulated burst-synchronizing signal to provide a rewriting pulse representing said second channel position in said burst; and a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and preselected channel unit signals from said transfer circuit to activate said identifier to produce a signal to energize said resampling generator to produce said another resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said predetermined signal portion placed in said second channel position in said burst.

Claim 18

A time division multiplex signaling system, comprising in combination: a transmitting terminal including: a source of input information signals; a multiplexer for converting said input information signals into time division multiplexed signal; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst and producing a signal for synchronizing said burst; carrier means for transmitting said predetermined signals including said burst-synchronizing signal; a memory channel specifier including a plurality of channel units; a first program-controlled processor for producing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store aid preassigned first channel position signal; said processor also transmitting in said transmitted carrier signals a signal representing said bust as identifying said transmitting terminal, a signal representing said preassigned first channel position in said burst and a signal representing said specifier preselected channel unit; a first timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; and a generator having signal comparators corresponding to said specifier channel units for comparing said first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals as corresponding to said preassigned first channel position signal; a receiving terminal incluDing: a receiver for said carrier-transmitted predetermined signals; means for demodulating said received carrier signals to provide reproductions of said predetermined signals, said burst-synchronizing signal, and said identifying burst, said first channel position and said preselected channel unit signals; means for decoding said reproduced predetermined signals to provide multiplexed information signals; means for demultiplexing said decoded multiplexed signals to distribute replicas of said input information signals as derived from said first channel position in said burst; a second program-controlled processor responsive to said reproduced burst, and first channel position and preselected channel unit signals for producing a signal representing said burst-identifying signal, a signal representing said preassigned first channel position in said burst, and a signal representing said preselected channel unit in said transmitting terminal specifier; a memory burst and channel identifier having channel units corresponding to said transmitting terminal specifier channel units for storing said burst and first channel position signals in such one of said identifier channel units as is preselected by said second processor channel unit signal; a second timing circuit responsive to said reproduced burst-synchronizing signal for deriving a burst-timing signal and a first channel position signal corresponding to said transmitting terminal burst and first channel position signals, respectively; and a generator having signal comparators corresponding to said identifier channel units for comparing said burst and first channel position signals stored in said preselected identifier channel unit with said second timing circuit derived burst and first channel position signals, respectively, for producing upon coincidence between said last-mentioned respective corresponding signals a resampling signal to activate said demultiplexing means to distribute said replicas of said input information signals as derived from said reproduced predetermined signals placed in said first channel position in said burst; and means for transmitting said input information signals as said predetermined signals in a preassigned second channel position in said burst and distributing said information signal replicas from said last-mentioned position at said receiving terminal, comprising: said transmitting terminal further including: said first processor responsive to a demand signal for changing channel positions as arising in said transmitting terminal to transmit said input information signals in a second channel position in said burst thereby being caused to produce a further first channel position signal, a signal representing said second channel position and a signal corresponding to said preselected specifier channel unit; said first processor also transmitting said identifying burst, said further first channel position, said second channel position and said preselected specifier channel unit signals in said carrier-transmitted signals; a first channel position memory circuit for storing said further first channel position signal and a second channel position memory circuit for storing said second channel position signal and said signal corresponding to preselected specifier channel unit; first and second channel position specifier memory circuits for comparing said further first and second channel position signals as stored in said respective first and second channel position memory circuits with said first timing circuit one channel position signal and a second channel position signal provided by said first timing circuit to produce output first and second channel position timing signals, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals; a predetermined signal memory circuit responsive to preassigned clock pulses, said first and second channel specifier memory circuit output first anD second signals, and said predetermined signals in the output of said encoding means for providing a portion of said last-mentioned signals for placement in said second channel position in said burst at the time of said first channel position signal; and a rewriting circuit activated by a rewriting pulse predetermined in time to represent said second channel position as produced by said first timing circuit to transfer said corresponding preselected channel unit signal from said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said sampling generator to provide a sampling signal to cause said multiplexing means to place said predetermined channel portion in said second channel position in said burst; said receiving terminal further including: said second processor responsive to said burst-identifying signal, said further first channel position signal, said second channel position signal and said corresponding channel unit signal as demodulated from said received carrier signals including said preselected signal portion placed in said second channel position in said burst to provide a burst signal representing said demodulated burst signal, a second channel position signal representing said preselected specifier channel unit; a transfer memory circuit for storing said last-mentioned burst second channel position and preselected channel unit signals; rewriting pulse-producing means for decoding said demodulated burst-synchronizing signal to produce a rewriting pulse representing said second channel position in said burst; and a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and preselected channel unit signals from said transfer circuit to activate said identifier to produce a signal to energize said resampling generator to produce a resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said demodulated

Claim 19

A time division multiplex signaling system, comprising in combination: a transmitting terminal including: a source of input information signals; a multiplexer for converting said input information signals into time division multiplexed signal; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst and producing a signal for synchronizing said burst; carrier means for transmitting said predetermined signals including said burst-synchronizing signal; a memory channel specifier including a plurality of channel units; a first program-controlled processor for producing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store aid preassigned first channel position signal; said processor also transmitting in said transmitted carrier signals a signal representing said bust as identifying said transmitting terminal, a signal representing said preassigned first channel position in said burst and a signal representing said specifier preselected channel unit; a first timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; and a generator having signal comparators corresponding to said specifier channel units for comparing said first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals as corresponding to said preassigned first channel position signal; a receiving terminal incluDing: a receiver for said carrier-transmitted predetermined signals; means for demodulating said received carrier signals to provide reproductions of said predetermined signals, said burst-synchronizing signal, and said identifying burst, said first channel position and said preselected channel unit signals; means for decoding said reproduced predetermined signals to provide multiplexed information signals; means for demultiplexing said decoded multiplexed signals to distribute replicas of said input information signals as derived from said first channel position in said burst; a second program-controlled processor responsive to said reproduced burst, and first channel position and preselected channel unit signals for producing a signal representing said burst-identifying signal, a signal representing said preassigned first channel position in said burst, and a signal representing said preselected channel unit in said transmitting terminal specifier; a memory burst and channel identifier having channel units corresponding to said transmitting terminal specifier channel units for storing said burst and first channel position signals in such one of said identifier channel units as is preselected by said second processor channel unit signal; a second timing circuit responsive to said reproduced burst-synchronizing signal for deriving a burst-timing signal and a first channel position signal corresponding to said transmitting terminal burst and first channel position signals, respectively; and a generator having signal comparators corresponding to said identifier channel units for comparing said burst and first channel position signals stored in said preselected identifier channel unit with said second timing circuit derived burst and first channel position signals, respectively, for producing upon coincidence between said last-mentioned respective corresponding signals a resampling signal to activate said demultiplexing means to distribute said replicas of said input information signals as derived from said reproduced predetermined signals placed in said first channel position in said burst; and means for transmitting said input information signals as said predetermined signals in a preassigned second channel position in said burst and distributing said information signal replicas from said last-mentioned position at said receiving terminal, comprising: said transmitting terminal further including: said first processor responsive to a demand signal for changing channel positions as arising in said transmitting terminal to transmit said input information signals in a second channel position in said burst thereby being caused to produce a further first channel position signal, a signal representing said second channel position and a signal corresponding to said preselected specifier channel unit; said first processor also transmitting said identifying burst, said further first channel position, said second channel position and said preselected specifier channel unit signals in said carrier-transmitted signals; a first channel position memory circuit for storing said further first channel position signal and a second channel position memory circuit for storing said second channel position signal and said signal corresponding to preselected specifier channel unit; first and second channel position specifier memory circuits for comparing said further first and second channel position signals as stored in said respective first and second channel position memory circuits with said first timing circuit one channel position signal and a second channel position signal provided by said first timing circuit to produce output first and second channel position timing signals, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals; a predetermined signal memory circuit responsive to preassigned clock pulses, said first and second channel specifier memory circuit output first anD second signals, and said predetermined signals in the output of said encoding means for providing a portion of said last-mentioned signals for placement in said second channel position in said burst at the time of said first channel position signal; and a rewriting circuit activated by a rewriting pulse predetermined in time to represent said second channel position as produced by said first timing circuit to transfer said corresponding preselected channel unit signal from said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said sampling generator to provide a sampling signal to cause said multiplexing means to place said predetermined channel portion in said second channel position in said burst; said receiving terminal further including: said second processor responsive to said burst-identifying signal, said further first channel position signal, said second channel position signal and said corresponding channel unit signal as demodulated from said received carrier signals including said preselected signal portion placed in said second channel position in said burst to provide a burst signal representing said demodulated burst signal, a second channel position signal representing said preselected specifier channel unit; a transfer memory circuit for storing said last-mentioned burst second channel position and preselected channel unit signals; rewriting pulse-producing means for decoding said demodulated burst-synchronizing signal to produce a rewriting pulse representing said second channel position in said burst; and a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and preselected channel unit signals from said transfer circuit to activate said identifier to produce a signal to energize said resampling generator to produce a resampling pulse to activate said demultiplexing means to distribute said information signal replicas as derived from said demodulated

Claim 20

A time division multiplex signal-transmitting terminal, comprising in combination: a source of input information signals; a multiplexer for converting said information signals into time division multiplexed signals; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst; carrier means for transmitting said predetermined signals in said burst; a memory channel specifier embodying a plurality of channel units; a program-controlled processor providing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store said preassigned first channel position signal; a timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; a generator having signal comparator corresponding to said specifier channel units for comparing said first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals corresponding to said preassigned first channel position signal; and means for transmitting said information signals encoded as said predetermined signals in a preassigned second channel position in said burst, comprising: said processor responsive to a demand signal arising in terminal to transmit said information signals in said second channel position in said burst thereby being caused to produce a furTher signal representing said first channel position, a signal representing said second channel position and a signal corresponding to said preselected specifier channel unit; and means responsive to said further first channel position signal and said second channel position signal occurring in coincidence with corresponding timing circuit first and second channel position signals for utilizing said predetermined signals at the output of said encoding means to derive said predetermined signals to be placed in said second channel position in said burst at the time of said further first channel position signal; said responsive means activated by a pulse produced at a predetermined time by said timing circuit as identifying said second channel position to apply said corresponding channel unit signal as produced by said processor to said specifier preselected channel unit to activate said last-mentioned unit to energize said generator to supply a sampling signal to cause said multiplexer to place said derived predetermined signals in said second channel position in said burst as transmitted by said carrier means.

Claim 21

A time division multiplex signal-transmitting terminal, comprising in combination: a source of input information signals; a multiplexer for converting said information signals into time division multiplexed signals; means for encoding said multiplexed signals into predetermined signals; a signal burst-forming circuit for arranging said predetermined signals in a channel position in a signal burst; carrier means for transmitting said predetermined signals in said burst; a memory channel specifier embodying a plurality of channel units; a program-controlled processor providing a signal preassigning a first channel position in said burst and a signal preselecting a channel unit in said specifier to store said preassigned first channel position signal; a timing circuit producing successively different channel position signals representing corresponding channel positions in said burst; a generator having signal comparator corresponding to said specifier channel units for comparing said first channel position signal stored in said preselected specifier channel unit with said timing circuit channel position signals for producing a sampling signal to activate said multiplexer to place said predetermined signals in said preassigned first channel position in said burst upon coincidence between said last-mentioned compared preassigned first channel position signal and one of said timing circuit channel position signals corresponding to said preassigned first channel position signal; and means for transmitting said information signals encoded as said predetermined signals in a preassigned second channel position in said burst, comprising: said processor responsive to a demand signal arising in terminal to transmit said information signals in said second channel position in said burst thereby being caused to produce a furTher signal representing said first channel position, a signal representing said second channel position and a signal corresponding to said preselected specifier channel unit; and means responsive to said further first channel position signal and said second channel position signal occurring in coincidence with corresponding timing circuit first and second channel position signals for utilizing said predetermined signals at the output of said encoding means to derive said predetermined signals to be placed in said second channel position in said burst at the time of said further first channel position signal; said responsive means activated by a pulse produced at a predetermined time by said timing circuit as identifying said second channel position to apply said corresponding channel unit signal as produced by said processor to said specifier preselected channel unit to activate said last-mentioned unit to energize said generator to supply a sampling signal to cause said multiplexer to place said derived predetermined signals in said second channel position in said burst as transmitted by said carrier means.

Claim 22

The transmitting terminal according to claim 15 in which said responsive means includes a first channel position memory circuit for storing said further first channel position signal and a second channel position memory circuit for storing said second channel position signal and said signal corresponding to said specifier preselected channel unit.

Claim 23

The transmitting terminal according to claim 16 in which said responsive means includes first and second channel position specifier memory circuits for comparing said further and second channel position signals stored in said first and second channel position memory circuits, respectively, with said timing circuit one channel position signal and a second channel position signal provided by said timing circuit to produce output first and second channel position timing signals, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals.

Claim 24

The transmitting terminal according to claim 17 in which said responsive means includes a predetermined signal memory circuit responsive to preassigned clock pulses, said first and second channel specifier memory circuit output first and second channel position timing signals and said predetermined signals taken from the output of said encoding means for deriving said predetermined signals to be placed in said second channel position in said burst at the time of said preassigned first channel position signal.

Claim 25

The transmitting terminal according to claim 18 in which said memory circuit comprises: an OR gate receiving said first and second channel specifier memory circuit input first and second channel position timing signals; a clock AND gate receiving clock pulses derived from said timing circuit and an output of said OR gate for producing stepping pulses lasting an eight-bit interval; a writing AND gate receiving said predetermined signals in the output of said encoding means and said second channel position specifier memory circuit output timing signal for deriving said predetermined signals to be placed in said second channel position from said encoding means output; an eight-stage shift register receiving said writing AND gate output and said eight-bit interval clock pulses for storing said predetermined signals taken from said decoding means output; and a reading AND gate receiving the output of said shift register and said first channel position specifier memory circuit output signal for reading out said predetermined signals stored in said shift register at the time of said preassigned first channel position signal.

Claim 26

The transmitting terminal according to claim 18 in which said responsive means includes a rewriting circuit activated by a rewriting pulse predetermined in time to represent said second channel position as produced by said timing circuit to transfer said signaL corresponding to said specifier preselected channel unit as stored in said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said generator to provide a sampling signal to energize said multiplexer to place said derived predetermined signals in said second channel position in said burst.

Claim 27

The transmitting terminal according to claim 15 in which said responsive means comprises: a first channel position memory circuit for storing said further first channel position signal and a second channel position memory circuit for storing said second channel position signal and said signal corresponding to said specifier preselected channel unit; first and second channel position specifier memory circuits for comparing said further and second channel stored in said respective first and second channel position memory circuits with said timing circuit one channel position signal and a second channel position signal provided by said timing circuit to produce output first and second channel position timing circuits, respectively, upon coincidence between said respective last-mentioned corresponding channel position signals; a predetermined signal memory circuit responsive to preassigned clock pulses derived from said timing circuit, said first and second channel specifier memory circuit output first and second channel position timing signals and said predetermined signals taken from the output of said encoding means for deriving said predetermined signals to be placed in said second channel position in said burst; and a rewriting circuit activated by a rewriting pulse predetermined in time to represent said second channel position as produced in said timing circuit to transfer said signal corresponding to said specifier preselected channel unit as stored in said second channel position memory circuit to said specifier preselected channel unit to activate said last-mentioned unit to energize said generator to provide q sampling signal to energize said multiplexer to place said derived predetermined signals in said second channel position in said burst.

Claim 28

A receiving terminal for information signals converted into time division multiplexed signals encoded into predetermined signals placed in preassigned first and second channel positions in a signal burst including a signal for synchronizing said burst, a signal identifying said burst, a signal representing said first channel position, a signal representing a preselected channel frame, a signal representing said second channel position and a further signal representing said first channel position in said burst for modulating a carrier wave, comprising in combination: a receiver for said signal-modulated carrier wave; means for demodulating said received signal-modulated carrier wave to reproduce said predetermined signals together with said burst-synchronizing, said burst-identifying, said first channel position, said preselected channel frame, said second channel position and said further first channel position signals; means for decoding said encoded predetermined signals in said first and second channel position into time division multiplexed signals corresponding to said first-mentioned time division multiplexed signals; a demultiplexer for distributing said decoded multiplexed signals as derived from said predetermined signals placed in said first and second channel positions into replicas of said first-mentioned information signals; a program-controlled processor responsive to said reproduced burst identification, said first channel position and said preselected channel frame signals for producing additional signals representing said respective last-mentioned signals; a memory burst and channel identifier having at least a channel unit corresponding to said additional channel frame signal and activated thereby for storing said additional burst identification and said first channel position signals; A timing circuit responsive to said reproduced burst synchronizing signal for deriving a burst-timing signal and a first channel position signal; a generator having at least a comparator corresponding to said identifier channel unit for comparing said additional burst and first channel position signals stored in said identifier channel unit with said respective timing circuit derived burst and first channel position signals for producing upon coincidence between said last-mentioned respective corresponding signals a sampling signal to activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said first channel position in said burst into replicas of said first-mentioned information signals; and means for activating said demultiplexer to distribute said multiplexed signals in the output of said demultiplexer as derived from said predetermined signals placed in said second channel position in said burst into other replicas of said first-mentioned information signals, consisting of: said processor further responsive to said reproduced further first channel position and said second channel position signals to produce other burst, second channel position and channel frame signals concurrently with said processor-produced additional burst and first channel position signals; and means responsive to said other burst, said second channel position and said channel frame signals together with a predetermined pulse derived from said reproduced burst-synchronizing signal in said timing circuit to represent said second channel position to activate said identifier to energize said generator to produce another sampling signal to activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said second channel position in said burst into additional replicas of said first-mentioned information signals.

Claim 29

A receiving terminal for information signals converted into time division multiplexed signals encoded into predetermined signals placed in preassigned first and second channel positions in a signal burst including a signal for synchronizing said burst, a signal identifying said burst, a signal representing said first channel position, a signal representing a preselected channel frame, a signal representing said second channel position and a further signal representing said first channel position in said burst for modulating a carrier wave, comprising in combination: a receiver for said signal-modulated carrier wave; means for demodulating said received signal-modulated carrier wave to reproduce said predetermined signals together with said burst-synchronizing, said burst-identifying, said first channel position, said preselected channel frame, said second channel position and said further first channel position signals; means for decoding said encoded predetermined signals in said first and second channel position into time division multiplexed signals corresponding to said first-mentioned time division multiplexed signals; a demultiplexer for distributing said decoded multiplexed signals as derived from said predetermined signals placed in said first and second channel positions into replicas of said first-mentioned information signals; a program-controlled processor responsive to said reproduced burst identification, said first channel position and said preselected channel frame signals for producing additional signals representing said respective last-mentioned signals; a memory burst and channel identifier having at least a channel unit corresponding to said additional channel frame signal and activated thereby for storing said additional burst identification and said first channel position signals; A timing circuit responsive to said reproduced burst synchronizing signal for deriving a burst-timing signal and a first channel position signal; a generator having at least a comparator corresponding to said identifier channel unit for comparing said additional burst and first channel position signals stored in said identifier channel unit with said respective timing circuit derived burst and first channel position signals for producing upon coincidence between said last-mentioned respective corresponding signals a sampling signal to activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said first channel position in said burst into replicas of said first-mentioned information signals; and means for activating said demultiplexer to distribute said multiplexed signals in the output of said demultiplexer as derived from said predetermined signals placed in said second channel position in said burst into other replicas of said first-mentioned information signals, consisting of: said processor further responsive to said reproduced further first channel position and said second channel position signals to produce other burst, second channel position and channel frame signals concurrently with said processor-produced additional burst and first channel position signals; and means responsive to said other burst, said second channel position and said channel frame signals together with a predetermined pulse derived from said reproduced burst-synchronizing signal in said timing circuit to represent said second channel position to activate said identifier to energize said generator to produce another sampling signal to activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said second channel position in said burst into additional replicas of said first-mentioned information signals.

Claim 30

The receiving terminal according to claim 22 in which said responsive means includes a transfer memory circuit for storing said other burst, second channel position and channel frame signals.

Claim 31

The receiving terminal according to claim 23 in which said responsive means includes rewriting pulse-producing means included in said timing circuit for decoding said reproduced burst-synchronizing signal to produce a rewriting pulse corresponding to said predetermined pulse derived from said last-mentioned signal in said timing circuit to represent said second channel position in said burst.

Claim 32

The receiving terminal according to claim 24 in which said responsive means includes a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and channel frame signals stored in said transfer memory circuit to activate said identifier to produce a signal to energize said generator to produce said another sampling signal to activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said second channel position in said burst, into said additional replicas of said first-mentioned information signals.

Claim 33

The receiving terminal according to claim 22 in which said responsive means includes: a transfer memory circuit for storing said other burst, second channel position and channel frame signals; rewriting pulse-producing means included in said timing circuit for decoding said reproduced burst-synchronizing signal to produce a rewriting pulse corresponding to said predetermined pulse derived from said last-mentioned signal in said timing circuit to represent said second channel position in said burst; and a rewriting circuit stimulated by said rewriting pulse to read out said burst, second channel position and channel frame signals stored in said transfer memory circuit to activate said identifier to produce a signal to energize said generator to produce said another sampling signal tO activate said demultiplexer to distribute said multiplexed signals in the output thereof as derived from said predetermined signals placed in said second channel position in said burst into said additional replicas of said first-mentioned information signals.