Signal recovery system for use with magnetic media

Claim 2

A data signal recovery system for recovering data signals recorded in a magnetic media and for converting same to electrical digital signals indicative of such recorded data signals, one bit of digital data being readable from said magnetic media in one-bit period, said recorded digital data being read back as a readback signal having first and second harmonically related signal components and shifts therebetween, the improvement including the combination: a linear amplifier receiving said readback signal and supplying an amplified signal, one-bit period circuit delay means receiving said readback signals and supplying same one-bit period later as a delayed signal linearly related in amplitude to said amplified signal at least at boundaries of said bit periods, absolute differencing circuit means receiving said amplified signal and said delayed signal and deriving the absolute difference amplitude therebetween in a linear manner, and supplying a third signal which is the absolute difference in amplitude between said amplified signal and said delayed signal, said third signal being characterized as having substantially all undulations in a same polarity with respect to a given reference potential and being of a frequency of only said first signal components, said signal components being suppressed, threshold generation means for generating a threshold voltage of the same polarity as said undulations of said third signal, a signal amplitude detector including amplitude comparison means receiving said threshold voltage and said third signal and supplying a first signal when said third signal has a predetermined amplitude relation to said threshold voltage, clock means receiving said delayed signal and generating gate pulses in timed relationship thereto, elapsed time between successively occurring gate pulses being a bit period, gating means receiving said comparator supplied first signal and said gate pulses, and being jointly responsive thereto to supply output pulses.

Claim 3

The subject matter of claim 1, wherein said absolute differencing circuit means comprises a differential amplifier receiving said amplified signal and said delayed signal, and supplying a different signal having the difference amplitude of said amplified and said delayed signal, full wave rectifier means receiving said difference signal and supplying said third signal, and said absolute difference circuit means including band pass filter means for passing said signal component frequencies.

Claim 4

The subject matter of claim 2, wherein said first signal component has a wavelength equal to twice the length of magnetic media scan during a given bit period, and said second signal component is an even harmonic of said first signal component, said clock means receiving said delayed signal and being responsive to said second signal component to generate said gate pulses intermediate successive ones of said bit periods.

Claim 5

The subject matter of claim 3, wherein said clock means includes reversing switch means for receiving said delayed signal, control means in said clock means responsive to a data pulse supplied by said signal amplitude detector to actuate said reversing switch means to pass a 180* phase-shIfted second signal component, and gate pulse generation means connected to said reversing switch means for receiving passed signal components therefrom and responsive thereto to generate the gate pulses.

Claim 6

The subject matter of claim 1, wherein said absolute differencing circuit means includes: a pair of phase splitting means respectively receiving said amplified signal and said delayed signal for supplying complementary and normal phases of said amplified and delayed signals, first linear summing means receiving the complementary phase of said amplified signal and normal phase of said delayed signal, second linear summing means receiving the complementary phase of said delayed signal and the normal phase of said amplified signal, positive OR means receiving said summed signals for supplying said third signal.

Claim 7

The system of claim 5, further including AC coupling means electrically interposed between said absolute differencing circuit means and said linear amplifier and one bit period circuit means for AC coupling said amplified signal and said delayed signal to said absolute differencing circuit means, and further AC coupling means electrically interposed between said phase-splitting means and said linear summing means respectively for AC coupling said normal and complementary phases of said amplified and delayed signals from said phase splitting means to said summing means, whereby base line shift in the detection of the readback signal is eliminated. 7 The subject matter of claim 1, further including: bistable control means responsive to said gate pulses for alternately supplying enabling and disabling signals over a pair of control lines, a pair of sample-and-hold circuit means respectively connected to said control lines and responsive to said enabling signal to perform linear amplifier summing functions and being further responsive to said disabling signal to hold a last occurring signal amplitude therein at least until receiving said enabling signal, said sample-and-hold circuits alternately acting as a linear amplifier and as a one-bit period circuit delay means and being connected to said absolute differencing circuit means for supplying said amplified signal and said delayed signal thereto and alternately and respectively serving the function of said linear amplifier and said one-bit period circuit delay means in alternately successive bit periods.

Claim 8

A data signal recovery system for recovering data signals recorded in a magnetic media and for converting such recovered digital data signals to electrical digital signals indicative of such recorded data signals, one bit of digital data being readable from said magnetic media in one bit period, said recorded digital data being read back as a readback signal having first and second harmonically related signal components and shifts therebetween, the improvement including the combination: a linear amplifier receiving said readback signal and supplying an amplified signal, one bit period linear delay means receiving said amplified signal and supplying a delayed signal having an amplitude substantially identical to said amplified signal but delayed by one of said bit periods, a pair of phase splitting means respectively receiving said amplified and said delayed signals and each supplying complementary and normal phases of said amplified and delayed signals, exclusive OR circuit means receiving said complementary and normal phases of said amplified and delayed signals and combining the complementary phase of one of said signals with the normal phase of the other signal, plus the complementary phase of said other signal with the normal phase of said one signal to supply a third signal having undulations all of the same polarity and characterized by having a frequency substantially all of said one signal component, a plurality of AC coupling means respectively and electrically interposed between said linear amplifiEr means and said pair of phase splitter means for AC coupling said readback and delayed signals to said phase splitting means and further AC coupling means respectively and electrically interposed between said phase splitting means and said exclusive OR circuit means for AC coupling said normal and complementary phases of said amplified and delayed signals to said exclusive OR circuit means such that base line shift in said third signal is eliminated, and amplitude detection means receiving said third signal and responsive to said third signal exceeding a predetermined amplitude in said given polarity to supply an output pulse.

Claim 9

A data signal recovery system for recovering data signals recorded in a magnetic media and for converting such recovered digital data signals to electrical digital signals indicative of such recorded data signals, one bit of digital data being readable from said magnetic media in one bit period, said recorded digital data being read back as a readback signal having first and second harmonically related signal components and shifts therebetween, the improvement including the combination: a linear amplifier receiving said readback signal and supplying an amplified signal, one bit period linear delay means receiving said amplified signal and supplying a delayed signal having an amplitude substantially identical to said amplified signal but delayed by one of said bit periods, a pair of phase splitting means respectively receiving said amplified and said delayed signals and each supplying complementary and normal phases of said amplified and delayed signals, exclusive OR circuit means receiving said complementary and normal phases of said amplified and delayed signals and combining the complementary phase of one of said signals with the normal phase of the other signal, plus the complementary phase of said other signal with the normal phase of said one signal to supply a third signal having undulations all of the same polarity and characterized by having a frequency substantially all of said one signal component, a plurality of AC coupling means respectively and electrically interposed between said linear amplifiEr means and said pair of phase splitter means for AC coupling said readback and delayed signals to said phase splitting means and further AC coupling means respectively and electrically interposed between said phase splitting means and said exclusive OR circuit means for AC coupling said normal and complementary phases of said amplified and delayed signals to said exclusive OR circuit means such that base line shift in said third signal is eliminated, and amplitude detection means receiving said third signal and responsive to said third signal exceeding a predetermined amplitude in said given polarity to supply an output pulse.

Claim 10

The subject matter of claim 8, further including clock channel means for successively generating gate pulses defining said bit periods, said clock channel including reversing switch means receiving said AC-coupled normal and complementary phases of said delayed signal and alternately supplying one of said phases as a synchronizing signal, gate pulse generator means responsive to said synchronizing signal to supply said gate pulses at a zero axis crossing of said synchronizing signal, and toggle circuit means receiving said output data pulses and connected to said reversing switch means for alternating the selection of said phases of said delayed signal to form said synchronizing signal each time an output data pulse is received.

Claim 11

The subject matter of claim 9, further including phase correction means coupled to said toggle means for toggling said reversing switch whenever the phase of said gate pulses is not consistent with the synchronizing signal, said means including an AND circuit jointly responsive to said gate pulses and to said synchronizing signal such that when the gate pulse is received whenever said synchronizing signal is of a predetermined polarity, the reversing switch is actuated to select the opposite phase of said delayed signal. 11. A signal recovery circuit for detecting a low frequency signal component from a signal having mixed low frequency and high frequency signal components with only one of said signal components occurring in a given bit period of recording data signal, the improvement including the combination: first and second sample-and-hold memory means operative when enabled to establish a stored signal amplitude appearing at an input portion thereof and further operative when disabled to linearly retain the last stored signal amplitude when last previously enabled at least until enabled again, clock means repetitively supplying clock signals identifying beginnings and ends of said bit periods, two-state means responsive to said clock pulses to change signal states alternately between first and second signal states, and connected to said memory means for enabling and disabling same, said first memory means being responsive to said first signal state to be enabled and to said second signal state to be disabled; said second memory means being responsive to said second signal state to be enabled and to said first signal state to be disabled, linear differencing means coupled to said memory means for differencing the stored signal amplitudes therein to supply a difference signal indicative of such difference, and amplitude detection means receiving said difference signal and being responsive thereto during said clock signal to supply an output signal whenever said difference signal exceeds a predetermined amplitude.