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US3597747A
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Digital memory system with ndro and dro portions
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1966-02-10
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Granted: 1971-08-03
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Expires: 1986-02-10
Abstract
Abstract A single hard core memory system is disclosed having a first portion capable of reading and writing information and a second portion having a capability of reading out information only. The memory described in a single memory system having common read means and common sense means which are common to both the destructive readout portion and the nondestructive readout portion.
Inventors
- 👤 Ted Winkler
- 👤 Paul E Wells
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:12
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/02
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
71 words
A digital memory system comprising: a plurality of identical memory elements; a nondestructive readout memory portion comprised of a first group of said memory elements; a destructive readout memory portion comprised of a second group of said memory elements; a common read means for applying a read signal to a selected one of said memory elements; and a common sense means responsive to switching in any one of said memory elements.
Claim 2
Dependent Claim
71 words
A digital memory system comprising: a plurality of identical memory elements; a nondestructive readout memory portion comprised of a first group of said memory elements; a destructive readout memory portion comprised of a second group of said memory elements; a common read means for applying a read signal to a selected one of said memory elements; and a common sense means responsive to switching in any one of said memory elements.
Claim 3
Dependent Claim
35 words
The memory system of claim 1 including means for electrically changing the ratio of the number of memory elements in said nondestructive readout portion to the number of memory elements in said destructive readout portions.
Claim 4
Dependent Claim
17 words
The memory system of claim 1 wherein each of said memory elements comprises a multiaperture magnetic core.
Claim 5
Dependent Claim
79 words
The memory system of claim 1 wherein each of said memory elements comprises a multiaperture magnetic core capable of defining a blocked state and first and second unblocked states; and wherein said nondestructive readout memory portion includes some elements defining said blocked state and said destructive readout memory portion includes elements only defining said first and second unblocked states wherein said read signal is effective only to switch the selected element from said second to said first unblocked state.
Claim 6
Dependent Claim
49 words
The memory system of claim 4 including block means for switching said memory elements to said blocked state, said block means including a block conductor coupled to each of said memory elements and a drive means adapted to be selectively connected to or physically separated from said block conductor.
Claim 7
Dependent Claim
39 words
The memory system of claim 4 including a common prime means for applying a prime signal to a selected one of said memory elements effective only to switch the selected element from said first to said second unblocked state.
Claim 8
Dependent Claim
45 words
The memory system of claim 6 including a binary drive means capable of defining first and second states; and means for inhibiting said prime signal from switching any memory element is said destructive readout portion in the event said drive means defines said second state.
Claim 9
Dependent Claim
77 words
The memory system of claim 7 wherein said memory elements are arranged in a rectangular matrix comprised of intersecting rows and columns, the elements of each row being coupled to a common row conductor and the elements of each column being coupled to a common column conductor; and wherein said read and prime signals are comprised of signals concurrently applied to a row conductor and a column conductor and effective at the element at the intersection thereof.
Claim 10
Dependent Claim
45 words
The memory system of claim 8 wherein said means for inhibiting said prime signals includes an inhibit conductor coupled to all of said elements in said destructive readout portion; and wherein said sense means includes a sense conductor coupled to all of said memory elements.
Claim 11
Dependent Claim
38 words
The memory system of claim 9 wherein each of said multiaperture cores comprises a transfluxor having a large and small aperture; and wherein said row and column conductors and said inhibit and sense conductors thread said small apertures.
Claim 12
Dependent Claim
58 words
The memory system of claim 10 including block means for switching said memory elements to said blocked state, said block means including a block conductor coupled to each of said memory elements and a drive means adapted to be selectively connected to or physically separated from said block conductor, said block conductor being threaded through said large apertures.
Claim 13
Dependent Claim
159 words
A digital memory system comprising: a plurality of identical memory elements each capable of defining either a blocked state or a first or second unblocked state; said plurality of memory elements being comprised of first and second ground of elements; means applying a read signal to a selected memory element effective only to switch said element from said second to said first unblocked state; binary sense means coupled to each of said plurality of memory elements and responsive to an element switching from said second to said first unblocked state for indicating a first state; binary drive means capable of defining first and second states; means applying a prime signal to a selected memory element effective only to switch said element from said first to said second unblocked state; and means inhibiting said prime signal from switching said selected memory element in the event said element is in said second group and said drive means defines said second state.
Claim 14
Dependent Claim
159 words
A digital memory system comprising: a plurality of identical memory elements each capable of defining either a blocked state or a first or second unblocked state; said plurality of memory elements being comprised of first and second ground of elements; means applying a read signal to a selected memory element effective only to switch said element from said second to said first unblocked state; binary sense means coupled to each of said plurality of memory elements and responsive to an element switching from said second to said first unblocked state for indicating a first state; binary drive means capable of defining first and second states; means applying a prime signal to a selected memory element effective only to switch said element from said first to said second unblocked state; and means inhibiting said prime signal from switching said selected memory element in the event said element is in said second group and said drive means defines said second state.
Claim 15
Dependent Claim
33 words
The memory system of claim 12 including means for electrically changing the ratio of the number of memory elements in said first group to the number of memory elements in said second group.
Claim 16
Dependent Claim
37 words
The memory system of claim 12 wherein said first group of memory elements includes at least some elements defining said blocked state and said second group includes elements defining only either said first or second unblocked states.
Claim 17
Dependent Claim
17 words
The memory system of claim 12 wherein each of said memory elements comprises a multiaperture magnetic core.
Claim 18
Dependent Claim
78 words
The memory system of claim 12 wherein said memory elements are arranged in a rectangular matrix compriSed of intersecting rows and columns, the elements of each row being coupled to a common row conductor and the elements of each column being coupled to a common column conductor; and wherein said read and prime signals are each comprised of signals concurrently applied to a row conductor and a column conductor and effective at the element at the intersection thereof.
Claim 19
Dependent Claim
44 words
The memory system of claim 12 wherein said means for inhibiting said prime signals includes an inhibit conductor coupled to all of said elements in said second group; and wherein said sense means includes a sense conductor coupled to all of said memory elements.
Claim 20
Independent Claim
194 words
A method of operating a digital memory system comprised of a plurality of memory elements each capable of defining a blocked state and first or second unblocked states to provide nondestructive and destructive readout portions, said method including the steps of; physically coupling a block signal source to all of said memory elements; causing said block signal source to provide a signal to all of said elements tending to switch them to said blocked state; inhibiting all of said elements in said destructive readout portion and selected elements in said nondestructive readout portion from switching to said blocked state to thereby enter data into said nondestructive readout portion; physically decoupling said block signal source from said memory elements; applying a prime signal to selected ones of said memory elements tending to switch said selected elements in an unblocked state to said second unblocked state; selectively inhibiting said prime signal from switching elements of said destructive readout portion to which it is applied to thereby enter data into said destructive readout portion; and applying a read signal to selected ones of said memory elements tending to switch said selected elements to said first unblocked state.
Claim 21
Independent Claim
194 words
A method of operating a digital memory system comprised of a plurality of memory elements each capable of defining a blocked state and first or second unblocked states to provide nondestructive and destructive readout portions, said method including the steps of; physically coupling a block signal source to all of said memory elements; causing said block signal source to provide a signal to all of said elements tending to switch them to said blocked state; inhibiting all of said elements in said destructive readout portion and selected elements in said nondestructive readout portion from switching to said blocked state to thereby enter data into said nondestructive readout portion; physically decoupling said block signal source from said memory elements; applying a prime signal to selected ones of said memory elements tending to switch said selected elements in an unblocked state to said second unblocked state; selectively inhibiting said prime signal from switching elements of said destructive readout portion to which it is applied to thereby enter data into said destructive readout portion; and applying a read signal to selected ones of said memory elements tending to switch said selected elements to said first unblocked state.
Claim 22
Dependent Claim
25 words
The method of claim 18 including the additional step of sensing to determine whether or not an element switches in response to said read signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-02 | 1975-02-01 | 1975-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-02 | 1979-02-01 | 1979-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-02 | 1983-02-01 | 1983-08-03 | $7700.00 | Window Closed / Lapsed |