Patent US3597640A successfully refreshed from Google Patents.
US3597640A
Expired / Lapsed
US
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Short circuit protection means for semiconductive circuit apparatus
Assignee: National Semiconductor Corp
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Filing: 1969-04-10
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Granted: 1971-08-03
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Expires: 1989-04-10
Abstract
Abstract A novel emitter debiasing integrated circuit transistor configuration for providing improved short circuit protection in the output stages of logic apparatus and the like. The spreading resistance of a semiconductor device is incorporated into the output current path of the output stage and the emitter and collector of the device are appropriately connected to shunt the load current through an alternative resistive path in the circuit should the current flow through the spreading resistance exceed a predetermined value which is determined by the emitter debiasing potential of the semiconductor device.
Inventors
- 👤 James J Kubinec
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
228 words
A logic circuit comprising: a first terminal for connection to a source of potential; a second terminal and a third terminal across which a load to be energized by said source of potential may be connected; a short circuit protection means including, a first body of semiconductive material of a first conductivity type; a second body of semiconductive material of a second conductivity type disposed contiguous with said first body and forming a first PN junction therebetween; a third body of semiconductive material of said first conductivity type disposed contiguous with said second body and forming a second PN junction therebetween; first metallic connector means ohmically contacting said first body; second metallic connector means ohmically contacting said second body and further ohimcally contacting one extremity of said third body; and third metallic connector means coupled to said second terminal and ohmically contacting an opposite extremity of said third body, whereby the spreading resistance of said third body between said first extremity and said opposite extremity provides a debiasing resistive shunt across said second PN junction; a resistor coupling said first connector means to said first terminal; first switching means responsive to an input signal and operative to couple saiD first connector means to said third terminal; and second switching means responsive to said first switching means and operative to couple said second connector means to said first terminal.
Claim 2
Dependent Claim
42 words
A logic circuit as recited in claim 2 and further comprising third switching means responsive to said first switching means and operative to couple said second terminal to said third terminal when said first switch means is in a particular switching state.
Claim 3
Dependent Claim
20 words
A logic circuit as recited in claim 2 wherein said second switching means includes a Darlington connected transistor switching circuit.
Claim 4
Dependent Claim
47 words
A logic circuit as recited in claim 2 wherein said first switching means includes a first transistor having a first base for receiving said input signal, a first emitter coupled to said third terminal, and a first collector coupled to said first connector means and said resistor.
Claim 5
Dependent Claim
45 words
A logic circuit as recited in claim 5 and further comprising a third switching means including a second transistor having a second base coupled to said first emitter, a second emitter coupled to said third terminal and a second collector coupled to said second terminal.
Claim 6
Dependent Claim
47 words
A logic circuit as recited in claim 5 wherein said second switching means includes a Darlington connected transistor switching circuit having a fourth terminal coupled to said first terminal, a fifth terminal coupled to said first collector, and a sixth terminal coupled to said second connector means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-02 | 1975-02-01 | 1975-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-02 | 1979-02-01 | 1979-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-02 | 1983-02-01 | 1983-08-03 | $7700.00 | Window Closed / Lapsed |