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US3597539A
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Frame synchronization system
Assignee: TDK Micronas GmbH
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Filing: 1968-12-04
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Granted: 1971-08-03
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Expires: 1988-12-04
Abstract
Abstract A binary information signal having a given bit rate and a local binary synchronization reference signal are applied to a digital comparison circuit, the output signal thereof indicating a match or mismatch between the binary conditions of successive adjacent bits of the information signal and the reference signal. A flipflop samples the output of the comparison circuit. A decision circuit responds to the samples from the flip-flop to produce binary ''''0'''' when the decision level is exceeded and binary ''''1'''' when the decision level is not exceeded. An AND gate coupled to the decision circuit and the comparison circuit provides an output signal only when the comparison circuit indicates a mismatch and the decision circuit produces binary ''''1'''' during halt time. This output signal is applied to an INHIBIT gate disposed between a bit rate clock and binary counters to change the counting of the counters to achieve synchronization in less time than required by prior art frame synchronization systems.
Inventors
- 👤 James M Clark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:33
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0617; H04L7/044; H04L7/046; H04L7/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
180 words
A frame synchronization system comprising: a source of binary information signal having a given bit rate and containing a synchronization component having a predetermined repetition frequency; first means to produce a plurality of timing signals, said timing signals including at least a sychronization reference signal in the form of a rectangular wave signal having a repetition frequency equal to said predetermined repetition frequency and a duration greater than the duration of said synchronization component; second means coupled to said source and said first means, said second means being responsive to said information signal and said reference signal to examine successive bits of said information signal within a given frame with respect to said reference signal to detect said synchronization component and produce a resultant output signal at each examination; and third means coupled to said second means and said first means, said third means being responsive to said resultant output signal to provide a control signal for timing adjustment of said timing signal of said first means when said resultant output signal indicates an out-of-synchronization condition until synchronization is achieved.
Claim 2
Dependent Claim
180 words
A frame synchronization system comprising: a source of binary information signal having a given bit rate and containing a synchronization component having a predetermined repetition frequency; first means to produce a plurality of timing signals, said timing signals including at least a sychronization reference signal in the form of a rectangular wave signal having a repetition frequency equal to said predetermined repetition frequency and a duration greater than the duration of said synchronization component; second means coupled to said source and said first means, said second means being responsive to said information signal and said reference signal to examine successive bits of said information signal within a given frame with respect to said reference signal to detect said synchronization component and produce a resultant output signal at each examination; and third means coupled to said second means and said first means, said third means being responsive to said resultant output signal to provide a control signal for timing adjustment of said timing signal of said first means when said resultant output signal indicates an out-of-synchronization condition until synchronization is achieved.
Claim 3
Dependent Claim
47 words
A system according to claim 1, wherein said second means includes digital comparison means coupled to said source and said first means to compare the binary condition of successive bits of said information signal and the binary condition of said reference signal and produce said resultant signal.
Claim 4
Dependent Claim
16 words
A system according to claim 2, wherein said digital comparison means includes an EXCLUSIVE OR circuit.
Claim 5
Dependent Claim
69 words
A system according to claim 2, wherein said first means includes a source of clock signal having said given rate, binary counter means, decoding means coupled to said counter means to produce said timing signals and said reference signal, and inhibit means coupled between said source of clock signal and said counter means and to said third means responsive to said control signal to carry out said timing adjustment.
Claim 6
Dependent Claim
66 words
A system according to claim 2, wherein said third means includes fourth means having a decision level coupled to said second means to produce a binary ''''1 '''' output when the voltage therein resulting from said resultant output signal is less than said decision level and a binary ''''0'''' output when the voltage therein resulting from said resultant output signal is greater than said decision level.
Claim 7
Dependent Claim
58 words
A system according to claim 5, wherein said third means further includes fifth means coupled to said fourth means and said second means to produce said control signal when said fourth means produces a binary ''''1'''' output and simultaneously said resultant output signal indicates a mismatch of the binary condition of said reference signal and said information signal.
Claim 8
Dependent Claim
23 words
A systeM according to claim 6, wherein said fifth means includes an AND circuit coupled to said fourth means and said second means.
Claim 9
Dependent Claim
48 words
A system according to claim 6, wherein said third means includes first bistable means triggered at said given bit rate coupled between said second means and said fourth means, and second bistable means triggered at said given bit rate coupled between said second means and said fifth means.
Claim 10
Dependent Claim
18 words
A system according to claim 8, wherein said first and second bistable means each include a flip-flop circuit.
Claim 11
Dependent Claim
186 words
A system according to claim 2, wherein said first means includes a source of clock signal having said given bit rate binary counter means, decoding means coupled to said counter means to produce said timing signals and said reference signal, and inhibit means coupled between said source of clock signal and said counter means; said digital comparison means includes an EXCLUSIVE OR: and said third means includes fourth means having a decision level coupled to said EXCLUSIVE OR to produce a binary ''''1'''' output when the voltage therein resulting from said resultant output signal is less than said decision level and a binary ''''0'''' output when the voltage therein resulting from said resultant output signal is greater than said decision level, and fifth means coupled to said fourth means and said EXCLUSIVE OR circuit to generate said control signal for coupling to said inhibit means to carry out said timing adjustment, said control signal being generated when said fourth means produces a binary ''''1'''' output and simultaneously said resultant output signal indicates a mismatch of the binary condition of said reference signal and said information signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-02 | 1975-02-01 | 1975-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-02 | 1979-02-01 | 1979-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-02 | 1983-02-01 | 1983-08-03 | $7700.00 | Window Closed / Lapsed |