Patent US3596115A successfully refreshed from Google Patents.
US3596115A
Expired / Lapsed
US
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Integrated monolithic semiconductor voltage regulator arrangement
Assignee: Robert Bosch GmbH
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Filing: 1969-04-24
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Granted: 1971-07-27
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Expires: 1989-04-24
Abstract
Abstract A monolithic semiconductor voltage regulator in which a lightly doped epitaxial layer is grown on a relatively heavily doped substrate. The electrical resistance of the epitaxial layer is high compared to that of the substrate. Power transistors and preamplifying transistors are formed within the monolithic semiconductor chip through isolation diffusion through the epitaxial layers. A first diffusion is then applied to the epitaxial layer within the isolation zone, and a second diffusion is applied within said first diffusion. The power transistor and the auxiliary transistors are structured so that they are complementary transistors. The power transistor may be formed as a substrate transistor and connected in common collector circuit. The doping substance for the substrate has a diffusion coefficient which is substantially lower than the diffusion coefficient of the doping substance used for the epitaxial layer.
Inventors
- 👤 Gerhard Conzelmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:00
CPC Classifications
H; H02; H02P; H02P9/00; H02P9/14; H02P9/26; H02P9/30; H02P9/305; H01; H01J; H01J29/00; H01J29/02; H01J29/023; H01J29/10; H01J29/36; H01J29/38; H01J29/385; H01J29/39; H01J29/44; H01J29/45; H01J29/458; H01J31/00; H01J31/08; H01J31/26; H01J31/48; H01J31/49; H01J31/50; H01J31/506; H01J31/52; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/617; H10D84/63; H10D84/641; H10D84/642
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
27 words
The monolithic semiconductor voltage regulator arrangement as defined in claim 1, including two said auxiliary transistors connected so that one conducts when the other is cut off.
Claim 2
Dependent Claim
225 words
A monolithic semiconductor voltage regulator arrangement for use with a voltage generator having an output, comprising, in combination, a substantially heavily doped substrate having relatively low electrical resistance; a substantially lightly doped epitaxial layer on said substrate and having a relatively high electrical resistance compared to said substrate, said substrate and said epitaxial layer being monolithic semiconductor means; at least one power transistor in said monolithic semiconductor means; first and second pairs of first and second auxiliary transistors in said monolithic semiconductor means, the collector of said first transistor of a pair being connected to the base of said second transistor of the same pair, the emitter of said second transistor of said first pair being connected to the base of said first transistor of said second pair, and emitter of said second transistor of said second pair being connected to the base of said power transistor so that the conductivity and nonconductivity of any one of said transistors is dependent on the conductive state of another one of said transistors; adjustable resistor means, external to said monolithic semiconductor means, connected across the output of said voltage generator; a zener diode connected to the base of said first transistor of said first pair and to said adjustable resistor means for rendering said first transistor of said first pair conductive when said zener diode is conductive.
Claim 3
Dependent Claim
191 words
A monolithic semiconductor voltage regulator arrangement for use with a voltage generator having an output, comprising, in combination, a substantially heavily doped substrate having relatively low electrical resistance; a substantially lightly doped epitaxial layer on said substrate and having a relatively high electrical resistance compared to said substrate, said substrate and said epitaxial layer being monolithic semiconductor means; first and second power transistors, Darlington Darlington connected, in said monolithic semiconductor means; a first emitter follower pair and a second emitter follower pair, connected together, in said monolithic semiconductor means, said second emitter follower pair being connected to the base of said first power transistor; voltage dividing means in said monolithic semiconductor means connected across said generator output; a zener diode and a plurality of temperature compensating diodes connected in series with said zener diode in said monolithic semiconductor means, said zener diode and said compensating diodes being connected between said first emitter follower pair and said voltage dividing means to render said first emitter follower pair conductive when said zener diode conducts; and temperature compensating resistor means, external to said monolithic semiconductor means, connected in parallel with said voltage dividing means.
Claim 4
Dependent Claim
14 words
The arrangement as defined in claim 4, wherein said power transistors are NPN type.
Claim 5
Dependent Claim
18 words
The arrangement as defined in claim 5, wherein said first and second emitter folloWer pairs are PNP transistors.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |