Pulse generating and timing circuit for providing accurately timed repetition of sequence of pulses

Claim 2

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation comprising: a positive and a negative terminal adapted to be connected to a source of direct current; a capacitor charging cIrcuit extending between said terminals; said capacitor charging circuit including a plurality of first resistors, a plurality of switches for selectively connecting a respective one of the first resistors to the positive terminal, a second resistor connected to the opposite ends of said first resistors from said switches, and a capacitor in circuit between said second resistor and said negative terminal; a common connection point; first and second diodes; and a pulse-forming resistor; a point in said capacitor charging circuit intermediate said first and second resistors being connected in the forward direction through said first diode to said common connection point; a first transistor having first emitter, collector and base electrodes; a second transistor of NPN type having second emitter, collector, and base electrodes; said first emitter electrode being connected to said capacitor charging circuit intermediate said capacitor and said second resistor; said first base electrode being connected through said second diode in the forward direction to said common connection point, said first collector electrode being connected to said second base electrode, said second collector electrode being connected to said common connection point, and said second emitter electrode being connected through said pulse-forming resistor to said negative terminal; and a voltage-divider network extending between said positive and negative terminals, said voltage divider network including third, fourth and fifth resistors in series, said third resistor extending from said positive terminal to said common connection point, said fourth resistor shunting said second diode, and said fifth resistor extending from said first base electrode to said negative terminal.

Claim 3

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation as claimed in Claim 1 in which the voltage pulses appearing across said pulse-forming resistor serve to actuate said switches in sequence for selectively connecting said first resistors individually into said capacitor charging circuit in sequence corresponding to said signal sequence.

Claim 4

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation as claimed in Claim 2 in which the ratio K between the time duration of successive signals of said signal sequence is determined by the sum of the resistances of said second resistor and one of said first resistors divided by the sum of the resistances of said second resistor and the successive one of said first resistors connected into said capacitor charging circuit.

Claim 5

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation as claimed in Claim 3 including a padding resistor shunting said fifth resistor for adjusting the time duration of the successive signals.

Claim 6

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation as claimed in Claim 3 including a stabilizing resistor connected from said first base electrode to said positive terminal for stabilizing the time duration of the signals in spite of changes in ambient conditions and in spite of fluctuations in the voltage of the source of current applied to said terminals.

Claim 7

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation comprising: a positive and a negative terminal adapted to be connected to a source of direct current; a capacitor charging circuit extending between said terminals; said capacitor charging circuit including a plurality of first resistors, a plurality of switches for selectively connecting a respective one of the first resistors to the positive terminal, a second resistor connected to the opposite ends of said first resistors from said switches, and a capacitor in circuit between said second resistor and Said negative terminal; a voltage divider network extending between said positive and negative terminal including a common connection point and a voltage-divider point intermediate the ends of said voltage divider network, said common connection point being in circuit nearer said positive terminal than said voltage-divider point; a first diode connected in the forward direction from a point in said capacitor charging network intermediate said first and second resistors to said common connection point; a second diode connected in the forward direction from said voltage-divider point to said common connection point; a pulse-forming resistor connected to said negative terminal; a first transistor having its emitter-to-base current flow path in circuit form a point in said capacitor charging circuit intermediate said capacitor and said second resistor to said voltage divider point, a second transistor of the NPN type having its collector to emitter current flow path in circuit between said common connection point and said pulse-forming resistor, and a connection from the collector electrode of the first transistor to the base electrode of said second transistor.

Claim 8

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation comprising: a positive and a negative terminal adapted to be connected to a source of direct current; a capacitor charging circuit extending between said terminals; said capacitor charging circuit including a plurality of first resistors, a plurality of switches for selectively connecting a respective one of the first resistors to the positive terminal, a second resistor connected to the opposite ends of said first resistors from said switches, and a capacitor in circuit between said second resistor and Said negative terminal; a voltage divider network extending between said positive and negative terminal including a common connection point and a voltage-divider point intermediate the ends of said voltage divider network, said common connection point being in circuit nearer said positive terminal than said voltage-divider point; a first diode connected in the forward direction from a point in said capacitor charging network intermediate said first and second resistors to said common connection point; a second diode connected in the forward direction from said voltage-divider point to said common connection point; a pulse-forming resistor connected to said negative terminal; a first transistor having its emitter-to-base current flow path in circuit form a point in said capacitor charging circuit intermediate said capacitor and said second resistor to said voltage divider point, a second transistor of the NPN type having its collector to emitter current flow path in circuit between said common connection point and said pulse-forming resistor, and a connection from the collector electrode of the first transistor to the base electrode of said second transistor.

Claim 9

A pulse generating and timing circuit for producing a predetermined signal sequence desirable for use in aids to navigation as claimed in claim 7 in which a padding resistor is shunted across the portion of said voltage divider network from said voltage-divider point to said negative terminal for adjusting the time duration of the signals of said sequence.

Claim 10

A pulse generating and timing circuit for producing a sequence of accurately timed pulses adapted to be employed in applications requiring reliable, accurately-timed pulses comprising a pair of terminals adapted to be connected to a source of direct current; a capacitor-charging circuit connected between said terminals; said capacitor-charging circuit including a capacitor to be charged and resistance means in circuit in series with the capacitor for controlling the rate at which said capacitor is charged; said capacitor-charging circuit including a point (M) in circuit intermediate said capacitor and resistance means; a voltage-divider network connected between said terminals; said voltage-divider network including a plurality of resistors; said voltage-divider network including a voltage-divider point (29) in circuit intermediate said resistors; a voltage-comparator and trigger circuit (15) connected between said capacitor-charging point (M) and said voltage-divider point (29); said voltage-comparator and trigger circuit including a pulse-forming resistor and a first transistor having its emitter-to-base current flow path in circuit from said capacitor-charging point (M) to said voltage-divider point (29), a second transistor of the NPN type having its collector-to-emitter current flow path in circuit from said resistance means in said capacitor-charging circuit to said pulse-forming resistor, and a connection from the collector electrode of the first transistor to the base electrode of said second transistor for suddenly discharging said capacitor through said resistor when the voltage of point (M) rises to a level above point (29) for generating voltage pulses across said resistor; and an output connection to said pulse-forming resistor for controlling a utilization circuit, by virtue of all of which the relative rate of charging of said capacitor is controlled by said resistance means in said capacitor-charging circuit and the actual time duration between pulses is controlled by said voltage-divider network.

Claim 11

A pulse generating and timing circuit for producing a sequence of accurately timed pulses adapted to be employed in applications requiring reliable, accurately-timed pulses comprising a pair of terminals adapted to be connected to a source of direct current; a capacitor-charging circuit connected between said terminals; said capacitor-charging circuit including a capacitor to be charged and resistance means in circuit in series with the capacitor for controlling the rate at which said capacitor is charged; said capacitor-charging circuit including a point (M) in circuit intermediate said capacitor and resistance means; a voltage-divider network connected between said terminals; said voltage-divider network including a plurality of resistors; said voltage-divider network including a voltage-divider point (29) in circuit intermediate said resistors; a voltage-comparator and trigger circuit (15) connected between said capacitor-charging point (M) and said voltage-divider point (29); said voltage-comparator and trigger circuit including a pulse-forming resistor and a first transistor having its emitter-to-base current flow path in circuit from said capacitor-charging point (M) to said voltage-divider point (29), a second transistor of the NPN type having its collector-to-emitter current flow path in circuit from said resistance means in said capacitor-charging circuit to said pulse-forming resistor, and a connection from the collector electrode of the first transistor to the base electrode of said second transistor for suddenly discharging said capacitor through said resistor when the voltage of point (M) rises to a level above point (29) for generating voltage pulses across said resistor; and an output connection to said pulse-forming resistor for controlling a utilization circuit, by virtue of all of which the relative rate of charging of said capacitor is controlled by said resistance means in said capacitor-charging circuit and the actual time duration between pulses is controlled by said voltage-divider network.

Claim 12

A pulse generating and timing circuit for producing a sequence of accurately timed pulses adapted to be employed in applications requiring reliable, accurately-timed pulses comprising a pair of terminals adapted to be connected to a source of direct current; a capacitor-charging circuit connected between said terminals; said capacitor-charging circuit including a capacitor to be charged and resistance means in circuit in series wiTh the capacitor for controlling the rate at which said capacitor is charged; said resistance means including a plurality of resistors; a plurality of switching elements connected to said resistors for selectively connecting said resistors into said capacitor-charging circuit for changing the rate at which said capacitor is charged; said capacitor-charging circuit including a point (M) in circuit intermediate said capacitor and resistance means; a voltage-divider network connected between said terminals; said voltage-divider network including a plurality of resistors; said voltage-divider network including a voltage-divider point (29) in circuit intermediate said resistors; a voltage-comparator and trigger circuit connected between said capacitor-charging point (M) and said voltage-divider point (29); said voltage-comparator and trigger circuit including a pulse-forming resistor for suddenly discharging said capacitor through said resistor when the voltage of point (M) rises to a level above point (29) for generating voltage pulses across said resistor; and an output connection to said pulse-forming resistor for controlling a utilization circuit, by virtue of all of which the relative rate of charging of said capacitor is controlled by said resistance means in said capacitor-charging circuit and the actual time duration between pulses is controlled by said voltage-divider network; and a connection from said pulse-forming resistor to said switching elements for selectively actuating them in response to the pulse generated.

Claim 13

A pulse generating and timing circuit for producing a sequence of accurately timed pulses adapted to be employed in applications requiring reliable, accurately-timed pulses comprising a pair of terminals adapted to be connected to a source of direct current; a capacitor-charging circuit connected between said terminals; said capacitor-charging circuit including a capacitor to be charged and resistance means in circuit in series wiTh the capacitor for controlling the rate at which said capacitor is charged; said resistance means including a plurality of resistors; a plurality of switching elements connected to said resistors for selectively connecting said resistors into said capacitor-charging circuit for changing the rate at which said capacitor is charged; said capacitor-charging circuit including a point (M) in circuit intermediate said capacitor and resistance means; a voltage-divider network connected between said terminals; said voltage-divider network including a plurality of resistors; said voltage-divider network including a voltage-divider point (29) in circuit intermediate said resistors; a voltage-comparator and trigger circuit connected between said capacitor-charging point (M) and said voltage-divider point (29); said voltage-comparator and trigger circuit including a pulse-forming resistor for suddenly discharging said capacitor through said resistor when the voltage of point (M) rises to a level above point (29) for generating voltage pulses across said resistor; and an output connection to said pulse-forming resistor for controlling a utilization circuit, by virtue of all of which the relative rate of charging of said capacitor is controlled by said resistance means in said capacitor-charging circuit and the actual time duration between pulses is controlled by said voltage-divider network; and a connection from said pulse-forming resistor to said switching elements for selectively actuating them in response to the pulse generated.