Patent US3595989A successfully refreshed from Google Patents.
US3595989A
Expired / Lapsed
US
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Dc-coupled chroma processing integrated circuit
Assignee: Lanteris Space LLC
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Filing: 1970-02-25
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Granted: 1971-07-27
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Expires: 1990-02-25
Abstract
Abstract A chroma-processing integrated circuit (IC) which provides an amplifier for a color television receiver''s chroma reference oscillator, buffers for said oscillator''s output, and X- and Zchroma demodulators. The output of said amplifier is direct current coupled, via the buffers, to the demodulators; thus no coupling capacitors, which would be external to the IC, are required. The buffers, which include appropriate AC and DC level shifting circuitry, also supply the chroma reference oscillator''s output to the receiver''s chroma kill and reference oscillator phase comparators. The transistors of the IC are temperature compensated by means of a network designed to shift the bias of said transistors, in response to temperature variations, in a direction which offsets the effect of such temperature variations.
Inventors
- 👤 Leander H Hoke Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:56
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/66
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
355 words
A chroma-processing integrated circuit for use in a color television receiver comprising: 1. an amplifying stage including at least one transistor and having a common terminal, an output terminal to which a tuned circuit can be connected, and an input terminal for receiving a feedback signal from said tuned circuit, thereby to provide an amplifier for a chroma-reference oscillator, 2. a first buffer stage comprising at least one transistor for providing isolation for the output of said amplifying stage, the output of said amplifying stage being direct current coupled to the input of said first buffer stage, 3. a second buffer stage, comprising at least one transistor, for providing isolation between an input terminal of said second buffer stage and a first demodulating stage, said first and second buffer stages arranged to provide direct current coupling from the output of said amplifying stage to said first demodulating stage when a direct current coupled phase-shifting circuit is connected between the output of said first buffer stage and the input of said second buffer stage, 4. said first demodulating stage including at least one transistor and having a first input terminal for receiving a chroma subcarrier signal, a second input terminal for receiving a first synchronous demodulating signal, and an output terminal for supplying a first color difference signal produced by a first mode of demodulation of said subcarrier, said output terminal of said second buffer stage being direct current coupled to said second input terminal of said first demodulating stage for supplying said first synchronous demodulating signal thereto, and 5. a second demodulating stage including at least one transistor and having a first input terminal for receiving said chroma subcarrier signal, a second input terminal for receiving a second synchronous demodulating signal, and an output terminal for supplying a second color difference signal produced by a second mode of demodulation of said subcarrier, said output terminal of said first buffer stage being direct current coupled to said second input terminal of said second demodulating stage, 6. the active and passive elements of all of the foregoing stages being comprised within a monocrystalline chip of semiconductive material.
Claim 2
Dependent Claim
355 words
A chroma-processing integrated circuit for use in a color television receiver comprising: 1. an amplifying stage including at least one transistor and having a common terminal, an output terminal to which a tuned circuit can be connected, and an input terminal for receiving a feedback signal from said tuned circuit, thereby to provide an amplifier for a chroma-reference oscillator, 2. a first buffer stage comprising at least one transistor for providing isolation for the output of said amplifying stage, the output of said amplifying stage being direct current coupled to the input of said first buffer stage, 3. a second buffer stage, comprising at least one transistor, for providing isolation between an input terminal of said second buffer stage and a first demodulating stage, said first and second buffer stages arranged to provide direct current coupling from the output of said amplifying stage to said first demodulating stage when a direct current coupled phase-shifting circuit is connected between the output of said first buffer stage and the input of said second buffer stage, 4. said first demodulating stage including at least one transistor and having a first input terminal for receiving a chroma subcarrier signal, a second input terminal for receiving a first synchronous demodulating signal, and an output terminal for supplying a first color difference signal produced by a first mode of demodulation of said subcarrier, said output terminal of said second buffer stage being direct current coupled to said second input terminal of said first demodulating stage for supplying said first synchronous demodulating signal thereto, and 5. a second demodulating stage including at least one transistor and having a first input terminal for receiving said chroma subcarrier signal, a second input terminal for receiving a second synchronous demodulating signal, and an output terminal for supplying a second color difference signal produced by a second mode of demodulation of said subcarrier, said output terminal of said first buffer stage being direct current coupled to said second input terminal of said second demodulating stage, 6. the active and passive elements of all of the foregoing stages being comprised within a monocrystalline chip of semiconductive material.
Claim 3
Dependent Claim
37 words
a first buffer stage comprising at least one transistor for providing isolation for the output of said amplifying stage, the output of said amplifying stage being direct current coupled to the input of said first buffer stage,
Claim 4
Dependent Claim
37 words
a first buffer stage comprising at least one transistor for providing isolation for the output of said amplifying stage, the output of said amplifying stage being direct current coupled to the input of said first buffer stage,
Claim 5
Dependent Claim
83 words
The integrated circuit of claim 1 further including a third buffer stage, comprising at least one transistor, for providing isolation between the output of said amplifying stage and the input of said first buffer stage, said third buffer stage providing direct coupling from the output of said amplifying stage and the input of said first buffer stage and including means for adjusting the direct current bias and alternating current signal levels present at the output of said amplifying stage by respectively different proportions.
Claim 6
Dependent Claim
85 words
said demodulating stages each include at least a second transistor, the emitter-collector path of which is connected to form a series circuit with the emitter-collector path of said first-named transistor, said chroma subcarrier signal being supplied to said second transistor of each of said demodulating stages to control the collector current in each of said second transistors, said first and second synchronous demodulating signals being supplied to said first transistor of each demodulating stage to control the collector current in each of said first transistors,
Claim 7
Dependent Claim
85 words
said demodulating stages each include at least a second transistor, the emitter-collector path of which is connected to form a series circuit with the emitter-collector path of said first-named transistor, said chroma subcarrier signal being supplied to said second transistor of each of said demodulating stages to control the collector current in each of said second transistors, said first and second synchronous demodulating signals being supplied to said first transistor of each demodulating stage to control the collector current in each of said first transistors,
Claim 8
Dependent Claim
55 words
said integrated circuit further including temperature-compensating means connected in common across the base-emitter circuits of said second transistors of said amplifying and demodulating stages, said means arranged to reduce temperature-induced variations in collector current of said second transistors by adjusting the bias of said transistors in a direction which counteracts said temperature-induced collector current variations.
Claim 9
Dependent Claim
55 words
said integrated circuit further including temperature-compensating means connected in common across the base-emitter circuits of said second transistors of said amplifying and demodulating stages, said means arranged to reduce temperature-induced variations in collector current of said second transistors by adjusting the bias of said transistors in a direction which counteracts said temperature-induced collector current variations.
Claim 10
Dependent Claim
33 words
The integrated circuit of claim 2 wherein said means for adjusting said bias and signal levels comprises a nonlinear circuit element connected in shunt with the signal path through said third buffer stage.
Claim 11
Dependent Claim
75 words
a second buffer stage, comprising at least one transistor, for providing isolation between an input terminal of said second buffer stage and a first demodulating stage, said first and second buffer stages arranged to provide direct current coupling from the output of said amplifying stage to said first demodulating stage when a direct current coupled phase-shifting circuit is connected between the output of said first buffer stage and the input of said second buffer stage,
Claim 12
Dependent Claim
75 words
a second buffer stage, comprising at least one transistor, for providing isolation between an input terminal of said second buffer stage and a first demodulating stage, said first and second buffer stages arranged to provide direct current coupling from the output of said amplifying stage to said first demodulating stage when a direct current coupled phase-shifting circuit is connected between the output of said first buffer stage and the input of said second buffer stage,
Claim 13
Dependent Claim
84 words
said first demodulating stage including at least one transistor and having a first input terminal for receiving a chroma subcarrier signal, a second input terminal for receiving a first synchronous demodulating signal, and an output terminal for supplying a first color difference signal produced by a first mode of demodulation of said subcarrier, said output terminal of said second buffer stage being direct current coupled to said second input terminal of said first demodulating stage for supplying said first synchronous demodulating signal thereto, and
Claim 14
Dependent Claim
84 words
said first demodulating stage including at least one transistor and having a first input terminal for receiving a chroma subcarrier signal, a second input terminal for receiving a first synchronous demodulating signal, and an output terminal for supplying a first color difference signal produced by a first mode of demodulation of said subcarrier, said output terminal of said second buffer stage being direct current coupled to said second input terminal of said first demodulating stage for supplying said first synchronous demodulating signal thereto, and
Claim 15
Dependent Claim
52 words
The integrated circuit of claim 1 further including temperature-compensating means connected across the base-emitter circuit of said transistor of said amplifying stage, said means arranged to reduce temperature-induced variations in collector current of said transistor by adjusting the bias of said transistor in a direction which counteracts said temperature-induced collector current variations.
Claim 16
Dependent Claim
75 words
a second demodulating stage including at least one transistor and having a first input terminal for receiving said chroma subcarrier signal, a second input terminal for receiving a second synchronous demodulating signal, and an output terminal for supplying a second color difference signal produced by a second mode of demodulation of said subcarrier, said output terminal of said first buffer stage being direct current coupled to said second input terminal of said second demodulating stage,
Claim 17
Dependent Claim
75 words
a second demodulating stage including at least one transistor and having a first input terminal for receiving said chroma subcarrier signal, a second input terminal for receiving a second synchronous demodulating signal, and an output terminal for supplying a second color difference signal produced by a second mode of demodulation of said subcarrier, said output terminal of said first buffer stage being direct current coupled to said second input terminal of said second demodulating stage,
Claim 18
Dependent Claim
7 words
The integrated circuit of claim 1 wherein
Claim 19
Dependent Claim
20 words
the active and passive elements of all of the foregoing stages being comprised within a monocrystalline chip of semiconductive material.
Claim 20
Dependent Claim
20 words
the active and passive elements of all of the foregoing stages being comprised within a monocrystalline chip of semiconductive material.
Claim 21
Dependent Claim
75 words
The integrated circuit of claim 1 further including temperature-compensating means connected in shunt with the direct current coupling between the output of said amplifying stage and said first buffer stage, said temperature-compensating means arranged to change the bias at the input of said first buffer stage in a direction, which when translated to said demodulating stages, tends to reduce temperature-induced collector current variations in the collector of each of said transistors of said demodulating stages.
Claim 22
Dependent Claim
14 words
The integrated circuit of claim 6 wherein said temperature-compensating means comprises unilaterally conductive means.
Claim 23
Dependent Claim
32 words
The integrated circuit of claim 1 wherein said amplifying stage includes means, responsive to a direct current control signal, for adjusting the phase and frequency of the output of said amplifying stage.
Claim 24
Dependent Claim
20 words
The integrated circuit of claim 8 wherein said means for adjusting the phase and frequency comprises a variable capacitance diode.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-26 | 1975-01-25 | 1975-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-26 | 1979-01-25 | 1979-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-26 | 1983-01-25 | 1983-07-27 | $7700.00 | Window Closed / Lapsed |