Counter actuated multiplex monitor circuit

Claim 2

A multiplex system for monitoring the performance of electrical apparatus wherein a plurality of comparator circuits are used to measure whether signals appearing at a plurality of test points within the apparatus have amplitudes within predetermined magnitude limits, where each of the comparator circuits normally produces a unipolar output signal only when the signal applied to the comparator is within the predetermined magnitude limits, comprising in combination: a plurality of bistable monitors, each of said plurality of monitors having an input, an output, reset means and enabling means, the input connected to receive the output signal from one of said comparators, the reset means operable upon receipt of a reset signal, to set each of said plurality of monitors into a first stable state, and the enabling means operable upon receipt of an enabling signal to enable a bipolar signal at said input to switch the monitor between stable states; timing means having an input and an output, the input of said timing means connected to the output of said plurality of bistable monitors to receive a signal therefrom, said timing means providing a signal at the timing means output when a predetermined time interval has elapsed without an input signal being applied at the timing means input; pulse generating means for producing an output pulse each time a monitor circuit switches from a first to a second stable state and also each time an output signal is produced by said timing means, said pulse generating means having an input and an output, with the input of said pulse generating means connected to the output of said plurality of bistable monitors and to the output of said timing means; a counter having an input and an output, the input of said counter connected to the output of said pulse generating means, the output of said counter connected to the enabling means of said plurality of monitors to sequentially and individually enable each Of said plurality of monitors; a first logic element connected to the output of said counter and generating a logical signal when the counter has received a number of pulses equal to the number of monitor circuits, the logic output of said first logic element connected to the reset means of said monitors; and a second logic element connected for receiving the output of said first logic element and the output of said pulse generating means and producing a logic output when a logic output is concurrently received from said first logic element and from said pulse generating means.

Claim 3

Apparatus of the class described in claim 1 wherein the output from said second logic element is passed to further means for producing an indication of the presence of a logic signal at the output of said second logic element.

Claim 4

Apparatus of the class described in claim 1 wherein a decade counter is connected to the output of said second logic element and is used to drive a numerical display to indicate the number of the comparison circuit which will supply the next pulse.

Claim 5

A circuit for indicating the absence of a bipolar signal at one or more of a plurality of test points, said circuit comprising in combination: a plurality of bistable monitor circuits, each of said bistable monitor circuits having an input, an output, reset means and enabling means, the input of each of said plurality of monitors connected to one of said plurality of test points to receive the signal therefrom, the reset means operable upon receipt of a reset signal to set each of said plurality of monitor means into a first stable state, enabling means operable to allow a bipolar signal at said input to switch the monitor between first and second stable states when an enabling signal is applied, the monitor producing a first output signal when switching from the first to the second state; a timer including an input and an output, the input of the timer connected to the output of said plurality of bistable monitors and producing a second output signal at the output when a predetermined time interval has elapsed without a signal being applied at the input means; first means for producing an output pulse signal each time the first output signal is received from said monitors and each time the second output signal is received from said timing means, said means including an output and also including an input connected to the output of said plurality of bistable monitors and to the output of said timer; a counter for generating enabling signals in response to input pulse signals, said counter including an input connected for receiving the pulse signal from the output of said first means and also including an output connected to the enabling means of said plurality of bistable monitors for applying enabling signals thereto to sequentially and individually enable each of said plurality of monitors; a first logic element for generating a logic output signal when the counter has received a number of pulses equal to the number of monitors, connected between the output of said counter and the reset means of said monitors; a second logic element connected to receive the output of the first logic element and the output of said first means, said second logic element producing a logic output when signals are concurrently received therefrom; and further electrical means connected for receiving the logic output of said second logic means, said further electrical means having an audible and a nonaudible indication, said further electrical means producing the audible indication until the logic output is received from said second logic element.

Claim 6

A circuit for indicating the absence of a bipolar signal at one or more of a plurality of test points, said circuit comprising in combination: a plurality of bistable monitor circuits, each of said bistable monitor circuits having an input, an output, reset means and enabling means, the input of each of said plurality of monitors connected to one of said plurality of test points to receive the signal therefrom, the reset means operable upon receipt of a reset signal to set each of said plurality of monitor means into a first stable state, enabling means operable to allow a bipolar signal at said input to switch the monitor between first and second stable states when an enabling signal is applied, the monitor producing a first output signal when switching from the first to the second state; a timer including an input and an output, the input of the timer connected to the output of said plurality of bistable monitors and producing a second output signal at the output when a predetermined time interval has elapsed without a signal being applied at the input means; first means for producing an output pulse signal each time the first output signal is received from said monitors and each time the second output signal is received from said timing means, said means including an output and also including an input connected to the output of said plurality of bistable monitors and to the output of said timer; a counter for generating enabling signals in response to input pulse signals, said counter including an input connected for receiving the pulse signal from the output of said first means and also including an output connected to the enabling means of said plurality of bistable monitors for applying enabling signals thereto to sequentially and individually enable each of said plurality of monitors; a first logic element for generating a logic output signal when the counter has received a number of pulses equal to the number of monitors, connected between the output of said counter and the reset means of said monitors; a second logic element connected to receive the output of the first logic element and the output of said first means, said second logic element producing a logic output when signals are concurrently received therefrom; and further electrical means connected for receiving the logic output of said second logic means, said further electrical means having an audible and a nonaudible indication, said further electrical means producing the audible indication until the logic output is received from said second logic element.

Claim 7

Signal deviation detection circuitry including input means for receiving a multiplicity of signals which may be divided into a plurality of signal groups to be monitored and also including output means, said signal deviation detection circuitry comprising, in combination: a plurality of multiplex means for receiving a group of input signals, sequentially monitoring each signal of said group of input signals for a required characteristic and providing a single bipolar output signal which has a first wave shape when each signal of said group of input signals has exhibited the required characteristic being monitored and has a second wave shape if one of the group of said input signals fails to exhibit the required characteristic after a predetermined interval; a plurality of indicator means each of which is connected by a single wire to one of said plurality of multiplex circuits for receiving the output signal therefrom, each of said indicator means responsive to the received signal to provide a sensory indication that one or more of the input signals has not exhibited the required characteristic.

Claim 8

Signal deviation detection circuitry including input means for receiving a multiplicity of signals which may be divided into a plurality of signal groups to be monitored and also including output means, said signal deviation detection circuitry comprising, in combination: a plurality of multiplex means for receiving a group of input signals, sequentially monitoring each signal of said group of input signals for a required characteristic and providing a single bipolar output signal which has a first wave shape when each signal of said group of input signals has exhibited the required characteristic being monitored and has a second wave shape if one of the group of said input signals fails to exhibit the required characteristic after a predetermined interval; a plurality of indicator means each of which is connected by a single wire to one of said plurality of multiplex circuits for receiving the output signal therefrom, each of said indicator means responsive to the received signal to provide a sensory indication that one or more of the input signals has not exhibited the required characteristic.

Claim 9

Apparatus of the class described in claim 5 wherein display means for determining which of the group of input signals received by a particular multiplex circuit of said plurality of said multiplex circuits has failed and wherein further means are provided for connecting the display means to receive the output signal of said particular multiplex circuit.