Digital pulse stretcher

Claim 2

A pulse stretcher for delaying and synchronizing a digital input input pulse comprising; an asynchronous pulse source for generating the digital pulse to be synchronized; a synchronous digital pulse frequency source to which the digital input pulse is to be synchronized; first, second and third bistable devices; means for operatively connecting said asynchronous pulse source to said first bistable device; means for operatively connecting said synchronous digital pulse source to said second bistable device; and, means for connecting said first and second bistable devices to said third bistable device whereby said third bistable device assumes a first state in response to the condition of said first bistable device and remains in said first state until changed by said second bistable device.

Claim 3

The pulse stretcher as recited in claim 1 further comprising a fourth bistable device operatively connected to said third bistable device and to said synchronous pulse source, said fourth bistable device being operative to assume a first state in response to the state of third bistable device and remain in said first state until the first pulse from said synchronous pulse source following a change in the state of said third bistable device.

Claim 4

The pulse stretcher recited in claim 1 wherein said asynchronous pulse source is an asynchronous circulating storage unit.

Claim 5

The pulse stretcher as recited in claim 3 wherein said asynchronous circulating storage unit comprises a delay line.

Claim 6

A serial data storage and processing system comprising: an asynchronous circulating circulating storage unit; a synchronous digital pulse frequency source; a pulse stretcher operatively connected to said asynchronous storage unit and said synchronous pulse source, said pulse stretcher including first, second, and third bistable devices operative to receive the outputs of said asynchronous storage unit and said synchronous pulse source so as to delay and synchronize the output of said asynchronous storage with the output of said synchronous pulse source; a serial data processor operatively connected to receive the output of said pulse stretcher; and means for connecting the output of said pulse stretcher to the input of said asynchronous storage unit.

Claim 7

A serial data storage and processing system comprising: an asynchronous circulating circulating storage unit; a synchronous digital pulse frequency source; a pulse stretcher operatively connected to said asynchronous storage unit and said synchronous pulse source, said pulse stretcher including first, second, and third bistable devices operative to receive the outputs of said asynchronous storage unit and said synchronous pulse source so as to delay and synchronize the output of said asynchronous storage with the output of said synchronous pulse source; a serial data processor operatively connected to receive the output of said pulse stretcher; and means for connecting the output of said pulse stretcher to the input of said asynchronous storage unit.

Claim 8

The serial data storage and processing system recited in claim 5 wherein said asynchronous circulating storage unit comprises a delay line.

Claim 9

A pulse stretcher for delaying and synchronizing a digital input pulse comprising: an asynchronous pulse source for generating the digital pulse to be synchronized; first, second, and third flip-flops, each having a set input terminal, a reset input terminal, a first output terminal for indicating when said flip-flop is set and a second output terminal for indicating when said flip-flop is reset; means for connecting the output of said asynchronous pulse source to said set input terminal of said first flip-flop; a first logic gate having its inputs connected to said asynchronous pulse source and to said first output terminal of said second flip-flop, the output of said first gate being connected to said reset input terminal of said first flip-flop and to said set input terminal of said third flip-flop; a second logic gate having its inputs connected to said first output of said first flip-flop and to said second input of said third flip-flop and its output connected to said set input terminal of said second flip-flop; a third logic Gate having its inputs connected to said synchronous pulse source and to said first output of said third flip-flop and its output connected to said reset input terminal of said second flip-flop; and, a fourth logic gate having its inputs connected to said second output of said second flip-flop and said output of said third gate and its input connected to said reset input terminal of said third flip-flop.

Claim 10

A pulse stretcher for delaying and synchronizing a digital input pulse comprising: an asynchronous pulse source for generating the digital pulse to be synchronized; first, second, and third flip-flops, each having a set input terminal, a reset input terminal, a first output terminal for indicating when said flip-flop is set and a second output terminal for indicating when said flip-flop is reset; means for connecting the output of said asynchronous pulse source to said set input terminal of said first flip-flop; a first logic gate having its inputs connected to said asynchronous pulse source and to said first output terminal of said second flip-flop, the output of said first gate being connected to said reset input terminal of said first flip-flop and to said set input terminal of said third flip-flop; a second logic gate having its inputs connected to said first output of said first flip-flop and to said second input of said third flip-flop and its output connected to said set input terminal of said second flip-flop; a third logic Gate having its inputs connected to said synchronous pulse source and to said first output of said third flip-flop and its output connected to said reset input terminal of said second flip-flop; and, a fourth logic gate having its inputs connected to said second output of said second flip-flop and said output of said third gate and its input connected to said reset input terminal of said third flip-flop.

Claim 11

The pulse stretcher recited in claim 7 further comprising a steered flip-flop having a set input connected to said first output of said third flip-flop, a reset input connected to said second output of said third flip-flop and a trigger input connected to said synchronous pulse source.

Claim 12

The pulse stretcher recited in claim 7 wherein said asynchronous pulse source comprises a delay line.

Claim 13

A serial data storage and processing system comprising: an asynchronous circulating storage unit, a source of recurrent clock pulses, means for circulating first and second data pulses in said circulating storage unit, the leading edge of said first pulse occurring after the leading edge of a first one of said clock pulses and a trailing edge occurring before the leading edge of a second one of said clock pulses, the leading edge of said second data pulse occurring after the leading edge of a second one of said clock pulses and the trailing edge occurring before the leading edge of a third one of said clock pulses, means responsive to the time of occurrence of the leading edge of said first data pulse to provide the leading edge of a modified first data pulse and to the trailing edge of said second one of said clock pulses to provide the trailing edge of said modified first data pulse, means responsive to the time of occurrence of the leading edge of said second data pulse to provide the leading edge of a modified second data pulse and to the trailing edge of said third one of said clock pulses to provide the trailing edge of the modified second data pulse, means responsive to the leading edge of said second data pulse occurring during the response of said first mentioned responsive means to said first data pulse for storing said second data pulse until the occurrence of the trailing edge of said second one of said clock pulses, means responsive to the leading edge of said modified first data pulse and the trailing edge of said second one of said clock pulses to provide the leading edge of a delayed first data pulse, means responsive to the trailing edge of said third one of said clock pulses to provide the trailing edge of said delayed first data pulse, means responsive to the leading edge of said stored second data pulse and the trailing edge of said third one of said clock pulses to provide the leading edge of a delayed second data pulse, means responsive to the trailing edge of a fourth one of said clock pulses to provide the trailing edge of said delayed second data pulse, means for processing said delayed first and second pulses to provide processed pulses, and means for circulating said processed pulses in said circulating storage unit.

Claim 14

A serial data storage and processing system comprising: an asynchronous circulating storage unit, a source of recurrent clock pulses, means for circulating first and second data pulses in said circulating storage unit, the leading edge of said first pulse occurring after the leading edge of a first one of said clock pulses and a trailing edge occurring before the leading edge of a second one of said clock pulses, the leading edge of said second data pulse occurring after the leading edge of a second one of said clock pulses and the trailing edge occurring before the leading edge of a third one of said clock pulses, means responsive to the time of occurrence of the leading edge of said first data pulse to provide the leading edge of a modified first data pulse and to the trailing edge of said second one of said clock pulses to provide the trailing edge of said modified first data pulse, means responsive to the time of occurrence of the leading edge of said second data pulse to provide the leading edge of a modified second data pulse and to the trailing edge of said third one of said clock pulses to provide the trailing edge of the modified second data pulse, means responsive to the leading edge of said second data pulse occurring during the response of said first mentioned responsive means to said first data pulse for storing said second data pulse until the occurrence of the trailing edge of said second one of said clock pulses, means responsive to the leading edge of said modified first data pulse and the trailing edge of said second one of said clock pulses to provide the leading edge of a delayed first data pulse, means responsive to the trailing edge of said third one of said clock pulses to provide the trailing edge of said delayed first data pulse, means responsive to the leading edge of said stored second data pulse and the trailing edge of said third one of said clock pulses to provide the leading edge of a delayed second data pulse, means responsive to the trailing edge of a fourth one of said clock pulses to provide the trailing edge of said delayed second data pulse, means for processing said delayed first and second pulses to provide processed pulses, and means for circulating said processed pulses in said circulating storage unit.

Claim 15

A serial data storage and processing system comprising: a circulating storage unit, a source of recurrent clock signals, means for circulating data pulses in said circulating storage unit, each said data pulse occurring between the leading edges of a preceding and a succeeding clock signal, means responsive to each data pulse to provide a modified data pulse at a subsequent period wherein the edge of said modified data pulse occurs at the trailing edge of the succeeding clock pulse and the trailing edge of said modified data pulse occurs at the trailing edge of the next clock pulse following the succeeding clock pulse, and means responsive to a data pulse occurring during the subsequent period associated with a previous date pulse to effectively delay said data pulse beyond said subsequent period before providing a modified data pulse thereof, means for processing said modified pulses and means for circulating said processed pulses in said circulating storage unit.

Claim 16

A serial data storage and processing system comprising: a circulating storage unit, a source of recurrent clock signals, means for circulating data pulses in said circulating storage unit, each said data pulse occurring between the leading edges of a preceding and a succeeding clock signal, means responsive to each data pulse to provide a modified data pulse at a subsequent period wherein the edge of said modified data pulse occurs at the trailing edge of the succeeding clock pulse and the trailing edge of said modified data pulse occurs at the trailing edge of the next clock pulse following the succeeding clock pulse, and means responsive to a data pulse occurring during the subsequent period associated with a previous date pulse to effectively delay said data pulse beyond said subsequent period before providing a modified data pulse thereof, means for processing said modified pulses and means for circulating said processed pulses in said circulating storage unit.