Shift register time compressor for sonar signal correlation

Claim 2

A sonar data correlator which comprises: a. a pair of spaced sonar receivers A and B having amplitude limiters connected thereto, b. a clock pulse source for producing pulses at the rate fc pulses per second, c. sampling means responsive to pulses from said source for sampling the polarity of signals from said receivers at the rate fc/2n, d. a shift register means for storing the samples from said sampling means and having n-1 stages and a recirculating loop, e. sample and hold means for providing reference samples of the signal from the first of said receivers at a first rate proportional to ffc/2nand for extracting samples of the signal from the second of said receivers from the last stage of said register means at a second rate proportional to fc/2, f. means to apply clock rate pulses to each stage of said register means to move said samples therethrough, g. a rapid writing display unit having a sweep triggered at intervals equal to n clock periods, and h. a polarity coincidence detector connected at one input to said last stage of said register means to receive A sample signals at said first rate, at the other input to receive B sample signals at said second rate, and at its output to the intensity modulation terminal of said display unit.

Claim 3

The combination of claim 1 wherein said register means comprises a single register with A and B samples interlaced therein and wherein a sample and hold unit is actuated to extract and hold B sample signals from a selected stage at said first rate for application to said detector.

Claim 4

The combination of claim 1 wherein said register means comprises two registers, one of which receives A sample signals and the other of which receives B sample signals.

Claim 5

A sonar data correlator which comprises: a. a pair of spaced sonar receivers A and B having amplitude limiters connected thereto, b. a clock pulse source for producing pulses at the rate of fc pulses per second, c. sampling means responsive to a pulses from said source for alternately sampling the polarity of signals from said receivers at a fc/2n rate, d. a shift register for storing the samples from said sampling means and having n-1 stages and a recirculating loop, e. sample and hold means for extracting and storing B sample signals from the receiver B a selected stage in said register at a fc/2n rate, f. means to apply clock pulses at the rate fc to each stage of said register to move said samples therethrough and extract A sample signals from receiver A from the last stage of said register at the rate of fc/2, g. a rapid writing display unit having a sweep triggered at intervals equal to n clock periods, and h. a polarity coincidence detector connected at one input to said last stage, at the other input to said sample and hold means, and at its output to the intensity modulation terminal of said display unit.

Claim 6

A sonar data correlator which comprises: a. a pair of spaced sonar receivers A and B having amplitude limiters connected thereto, b. a clock pulse source for producing pulses at the rate of fc pulses per second, c. sampling means responsive to a pulses from said source for alternately sampling the polarity of signals from said receivers at a fc/2n rate, d. a shift register for storing the samples from said sampling means and having n-1 stages and a recirculating loop, e. sample and hold means for extracting and storing B sample signals from the receiver B a selected stage in said register at a fc/2n rate, f. means to apply clock pulses at the rate fc to each stage of said register to move said samples therethrough and extract A sample signals from receiver A from the last stage of said register at the rate of fc/2, g. a rapid writing display unit having a sweep triggered at intervals equal to n clock periods, and h. a polarity coincidence detector connected at one input to said last stage, at the other input to said sample and hold means, and at its output to the intensity modulation terminal of said display unit.

Claim 7

In a sonar system where acoustic energy from a source of unknown bearing is sensed at two spaced apart detecting stations, the combination which comprises: a. a pair of exclusive OR units, the first of which is connected to the Second, b. a limiter connected between the first detecting station and the first exclusive OR unit, c. a limiter connected between the second detecting station and the first exclusive OR unit, d. a shift register of n-1 stages having an input connected to the second exclusive OR unit and a recirculating loop leading to said second exclusive OR unit, e. a sample selector gate connected to the last stage of said shift register, f. a sample selector and hold unit connected at one input to an intermediate stage of said shift register, g. a display unit having an intensity control input and a sweep input, h. clock means for applying pulses at the rate fc to all stages of said register, at the rate fc/n to said sample and hold unit, at the rate fc/2n to said first exclusive OR unit and to said sample selector gate, at the rate fc/n to said second exclusive OR unit and to said sweep input, and i. a polarity coincidence detector connected at its inputs to said sample selector gate and to said sample selector and hold unit and at its output to said intensity control input.

Claim 8

In a sonar system where acoustic energy from a source of unknown bearing is sensed at two spaced apart detecting stations, the combination which comprises: a. a pair of exclusive OR units, the first of which is connected to the Second, b. a limiter connected between the first detecting station and the first exclusive OR unit, c. a limiter connected between the second detecting station and the first exclusive OR unit, d. a shift register of n-1 stages having an input connected to the second exclusive OR unit and a recirculating loop leading to said second exclusive OR unit, e. a sample selector gate connected to the last stage of said shift register, f. a sample selector and hold unit connected at one input to an intermediate stage of said shift register, g. a display unit having an intensity control input and a sweep input, h. clock means for applying pulses at the rate fc to all stages of said register, at the rate fc/n to said sample and hold unit, at the rate fc/2n to said first exclusive OR unit and to said sample selector gate, at the rate fc/n to said second exclusive OR unit and to said sweep input, and i. a polarity coincidence detector connected at its inputs to said sample selector gate and to said sample selector and hold unit and at its output to said intensity control input.

Claim 11

The method of claim 6 wherein said samples pass through the same shift register as an interlaced time series.