Patent US3594585A successfully refreshed from Google Patents.
US3594585A
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Pulse recognition circuit
Assignee: EAGLE SIGNAL CONTROLS CORP A CORP OF
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Filing: 1968-05-31
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Granted: 1971-07-20
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Expires: 1988-05-31
Abstract
Abstract The disclosure describes a circuit capable of recognizing a succession of changes in an electrical signal and of discriminating against signals having amplitude, duration or fall times which lie outside predetermined values. The circuit requires no separate power supply, relaying on the input signal for its power supply and thus consuming no power during standby, and provides a combination of elements which is sensitive to voltage level changes appearing at discrete time intervals.
Inventors
- 👤 Joseph A Bourget
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:52
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
304 words
A pulse recognition circuit responsive only to an input pulse having predetermined amplitude, duration, and fall time characteristics, comprising: an input for receiving an input pulse; first timing circuit means having a time constant less than the duration of said input pulse and connected to said input for producing a first voltage proportional to the amplitude and duration of said input pulse; second timing circuit means having a time constant greater than the duration of said input pulse and connected to said input for producing a second voltage proportional to the amplitude and duration of said input pulse; third timing circuit means including a charge and discharge circuit connected to said input, said third timing circuit having a time constant slightly longer than the said predetermined fall time of said input pulse for producing a third voltage which closely follows the fall time of said input pulse; output means including first switch means having input, output and control electrodes, said first timing circuit means being connected to said input electrode and said third timing means being connected to said control electrode, whereby said first and third voltages are applied to said input and control electrodes, respectively, and follow the voltage of said input pulse during its rise time and duration, said output means thereafter becoming operative to produce an output pulse only when the fall time of said input pulse has said predetermined characteristic so that said third voltage falls below said first voltage by a predetermined amount; and second switch means connected to said first timing circuit means and responsive to said second voltage for disabling said first timing circuit when said second voltage exceeds a predetermined value corresponding to a selected maximum duration for said input pulse, whereby said output pulse is produced only when said input pulse has said predetermined characteristics.
Claim 2
Dependent Claim
304 words
A pulse recognition circuit responsive only to an input pulse having predetermined amplitude, duration, and fall time characteristics, comprising: an input for receiving an input pulse; first timing circuit means having a time constant less than the duration of said input pulse and connected to said input for producing a first voltage proportional to the amplitude and duration of said input pulse; second timing circuit means having a time constant greater than the duration of said input pulse and connected to said input for producing a second voltage proportional to the amplitude and duration of said input pulse; third timing circuit means including a charge and discharge circuit connected to said input, said third timing circuit having a time constant slightly longer than the said predetermined fall time of said input pulse for producing a third voltage which closely follows the fall time of said input pulse; output means including first switch means having input, output and control electrodes, said first timing circuit means being connected to said input electrode and said third timing means being connected to said control electrode, whereby said first and third voltages are applied to said input and control electrodes, respectively, and follow the voltage of said input pulse during its rise time and duration, said output means thereafter becoming operative to produce an output pulse only when the fall time of said input pulse has said predetermined characteristic so that said third voltage falls below said first voltage by a predetermined amount; and second switch means connected to said first timing circuit means and responsive to said second voltage for disabling said first timing circuit when said second voltage exceeds a predetermined value corresponding to a selected maximum duration for said input pulse, whereby said output pulse is produced only when said input pulse has said predetermined characteristics.
Claim 3
Dependent Claim
35 words
The pulse recognition circuit of claim 1, wherein said outpuT means is a first transistor, said transistor being normally nonconductive but becoming conductive when said first voltage exceeds said third voltage by said predetermined amount.
Claim 4
Dependent Claim
55 words
The pulse recognition circuit of claim 2, wherein said output means further includes a second transistor having a control electrode connected through a voltage divider to the output electrode of said first transistor, said second transistor being normally nonconductive but becoming conductive when said first transistor conducts and said first voltage exceeds said predetermined voltage.
Claim 5
Dependent Claim
58 words
The pulse recognition circuit of claim 1, wherein each of said first, second, and third timing circuit means for producing said first, second and third voltages, respectively, comprises a resistive-capacitive network for receiving energy from said input pulse, said capacitors storing said received energy to provide bias voltages for said circuit, whereby no external power supply is required.
Claim 6
Dependent Claim
39 words
The pulse recognition circuit of claim 4, wherein said second switch means for disabling said first timing circuit means comprises a pulse duration limit switch responsive to said second voltage to discharge the capacitor of said first resistive-capacitive network.
Claim 7
Dependent Claim
52 words
The pulse recognition circuit of claim 5, wherein said pulse duration limit switch comprises a transistor connected across the capacitor of said first resistive-capacitive network, said transistor being normally nonconductive and responsive to a predetermined level of said second voltage to switch to its conductive state, thereby to discharge said last-named capacitor.
Claim 8
Dependent Claim
16 words
The pulse recognition circuit of claim 1, wherein said output means comprises a regenerative latching switch.
Claim 9
Dependent Claim
46 words
The pulse recognition circuit of claim 10, wherein said latching switch includes said first switch means and a third, complementary switch means, said first and third switch means becoming operative to produce said output pulse only when said input pulse has all of said predetermined values.
Claim 10
Dependent Claim
24 words
The pulse recognition circuit of claim 7, wherein each of said first, second and third timing circuit means includes a passive pulse storage means.
Claim 11
Dependent Claim
38 words
The pulse recognition circuit of claim 9, wherein said first passive storage means stores energy from said input pulse to provide a bias voltage for said output means, whereby said pulse recognition circuit requires no external power supply.
Claim 12
Dependent Claim
22 words
The pulse recognition circuit of claim 9, wherein said first, second and third timing circuit means each comprises a resistor-capacitor storage network.
Claim 13
Dependent Claim
50 words
The pulse recognition circuit of claim 11, wherein said second switch means comprises a first transistor connected across the capacitor of said first timing circuit, said latching switch and said first timing circuit being disabled by discharge of the capacitor in said first timing circuit through conduction of said transistor.
Claim 14
Dependent Claim
19 words
The pulse recognition circuit of claim 12, wherein said first and third switch means comprise second and third transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-19 | 1975-01-18 | 1975-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-19 | 1979-01-18 | 1979-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-19 | 1983-01-18 | 1983-07-20 | $7700.00 | Window Closed / Lapsed |