Zero crossing detector

Claim 2

A zero crossing detector for producing an output pulse in response to a zero crossing of an input signal comprising first polarity sensing means connected to receive said input signal for producing an output when said input signal is of a first polarity, a clock oscillator for producing a series of timing pulses, a pulse divider for producing an output pulse in response to an even number of input pulses, first gating means having inputs connected to said clock oscillator and said first polarity sensing means respectively, and an output connected to said pulse divider for passing said timing pulses to said pulse divider in response to an absence of output from said first polarity sensing means, and reset means connected between said pulse divider and said first gating means for blocking said timing pulses in response to an output pulse from said pulse divider.

Claim 3

A zero crossing detector as in claim 1 including second polarity sensing means connected to receive said input signal for producing an output when said input signal is of a second polarity, and second gating means having inputs connected to said clock oscillator, said second polarity sensing means, and said reset means, respectively, and an output connected to said pulse divider for passing said timing pulses to said pulse divider in response to an absence of output from said second polarity sensing means, wherein said reset means alternately blocks and reset said first and second gating means in phase opposition in response to successive output pulses from said pulse divider.

Claim 4

A zero crossing detector as in claim 2 wherein said reset means comprises a toggle flip-flop having an input connected to the output of said pulse divider, a first output connected to an input of said first gating means, and a second output of opposite phase to said first output connected to an input of said second gating means.

Claim 5

A zero crossing detector as in claim 3 including a first AND gate having a first input connected to said first polarity sensing means, a second input connected to said toggle flip-flop first output and an output connected to said first gating means, and a second AND gate Having a first input connected to said second polarity sensing means, a second input connected to said toggle flip-flop second output and an output connected to said second gating means whereby said first and second AND gates are disabled during said output pulses.

Claim 6

Apparatus for emitting a pulse at an output in response to each zero crossing of an AC input signal comprising rectifying means for emitting a first signal corresponding to the positive part of said AC input signal and a second signal corresponding to the negative part of said AC input signal; a first AND gate having a first input connected to receive said first signal, a second input and an output; a second AND gate having a first input connected to receive said second signal, a second input and an output; a first signal inverter connected to the output of said first AND gate; a second signal inverter connected to the output of said second AND gate; a clock oscillator for producing a series of uniform pulses; a third AND gate having a first input connected to the output of said first signal inverter, a second input connected to the output of said clock oscillator, a third input and an output for passing pulses from said clock oscillator when said three third AND gate inputs are enabled; a fourth AND gate having a first input connected to the output of said second inverter, a second input connected to the output of said clock oscillator, a third input and an output for passing pulses from said clock oscillator when said three fourth AND gate inputs are enabled; a first bistable multivibrator having a toggle input connected to the outputs of said third and fourth AND gates and an output connected to said output terminal; a second bistable multivibrator having a toggle input connected to said output terminal, a first output connected to the second input of said first AND gate and the third input of said third AND gate and a second output of opposite phase connected to the second input of said second AND gate and the third input of said fourth AND gate, whereby said third and fourth AND gates are inhibited after passing two pulses from said clock oscillator, and said first and second AND gates are inhibited during said output pulse.

Claim 7

Apparatus for emitting a pulse at an output in response to each zero crossing of an AC input signal comprising rectifying means for emitting a first signal corresponding to the positive part of said AC input signal and a second signal corresponding to the negative part of said AC input signal; a first AND gate having a first input connected to receive said first signal, a second input and an output; a second AND gate having a first input connected to receive said second signal, a second input and an output; a first signal inverter connected to the output of said first AND gate; a second signal inverter connected to the output of said second AND gate; a clock oscillator for producing a series of uniform pulses; a third AND gate having a first input connected to the output of said first signal inverter, a second input connected to the output of said clock oscillator, a third input and an output for passing pulses from said clock oscillator when said three third AND gate inputs are enabled; a fourth AND gate having a first input connected to the output of said second inverter, a second input connected to the output of said clock oscillator, a third input and an output for passing pulses from said clock oscillator when said three fourth AND gate inputs are enabled; a first bistable multivibrator having a toggle input connected to the outputs of said third and fourth AND gates and an output connected to said output terminal; a second bistable multivibrator having a toggle input connected to said output terminal, a first output connected to the second input of said first AND gate and the third input of said third AND gate and a second output of opposite phase connected to the second input of said second AND gate and the third input of said fourth AND gate, whereby said third and fourth AND gates are inhibited after passing two pulses from said clock oscillator, and said first and second AND gates are inhibited during said output pulse.