Patent US3593044A successfully refreshed from Google Patents.
US3593044A
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Bit synchronization arrangement for pcm systems
Assignee: International Standard Electric Corp
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Filing: 1969-08-26
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Granted: 1971-07-13
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Expires: 1989-08-26
Abstract
Abstract The local bit clock is provided by an astable multivibrator having a varactor diode included in the cross coupling thereof to adjust the phase of the bit clock. A variable-width pulse is derived from the phase relation of a nonreturn-to-zero PCM signal and the local clock. A constant width pulse of one-bit clock period is derived from the PCM signal and inverted. These two pulse signals are algebraically combined and integrated to provide a control bias to adjust the bias of the varactor diode and, hence, clock phase to achieve and maintain bit synchronization.
Inventors
- 👤 Joseph Hood Mcneilly
- 👤 Paul Barton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H03; H03L; H03L7/00; H03L7/06; H04L7/027
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
150 words
A bit synchronization arrangement for a PCM system comprising: a source of PCM signal; first means to produce local bit clock pulses; second means coupled to said source and said first means to produce variable-width pulses of given polarity, the width of said variable-width pulses being determined by the phase relationship between said PCM signal and said local clock pulses; third means coupled to said second means to produce constantwidth pulses having a polarity opposite said given polarity, the width of said constant-width pulses being equal to a period of said local clock pulses; fourth means coupled to said second and third means to algebraically combine said variable-width and constant-width pulses and produce a control voltage; and fifth means coupled to said first and fourth means to apply said control voltage to said first means to adjust the phase of said local clock pulses to achieve and maintain bit synchronization.
Claim 2
Dependent Claim
150 words
A bit synchronization arrangement for a PCM system comprising: a source of PCM signal; first means to produce local bit clock pulses; second means coupled to said source and said first means to produce variable-width pulses of given polarity, the width of said variable-width pulses being determined by the phase relationship between said PCM signal and said local clock pulses; third means coupled to said second means to produce constantwidth pulses having a polarity opposite said given polarity, the width of said constant-width pulses being equal to a period of said local clock pulses; fourth means coupled to said second and third means to algebraically combine said variable-width and constant-width pulses and produce a control voltage; and fifth means coupled to said first and fourth means to apply said control voltage to said first means to adjust the phase of said local clock pulses to achieve and maintain bit synchronization.
Claim 3
Dependent Claim
40 words
An arrangement according to claim 1, wherein said first means includes an astable multivibrator having a cross-coupling circuit between the stages thereof including a varactor diode responsive to said control voltage to adjust the phase of said local clock pulses.
Claim 4
Dependent Claim
62 words
An arrangement according to claim 1, wherein said second means includes a shift register coupled to said source and said first means, said PCM signal being shifted into said shaft register under control of said local clock pulses, and first gate means coupled to said source and an output from the first stage of said shift register to produce said variable-width pulses.
Claim 5
Dependent Claim
42 words
An arrangement according to claim 3, wherein said third means includes second gate means coupled to an output from the first stage of said shift register and an output from the second stage of said shift register to produce said constant-width pulses.
Claim 6
Dependent Claim
25 words
An arrangement according to claim 1, wherein said fourth means includes a capacitor coupled to said second and third means to produce said control voltage.
Claim 7
Dependent Claim
16 words
An arrangement according to claim 5, further including a constant voltage source coupled to said capacitor.
Claim 8
Dependent Claim
27 words
An arrangement according to claim 1, wherein said fifth means includes an amplifier coupled to said fourth means to apply said control voltage to said firSt means.
Claim 9
Dependent Claim
178 words
An arrangement according to claim 1, wherein said first means includes an astable multivibrator having a cross-coupling circuit between the stages thereof including a varactor diode responsive to said control voltage to adjust the phase of said local clock pulses; said second means includes a shift register coupled to said source and said first means, said PCM signal being shifted into said shift register under control of said local clock pulses, and first gate means coupled to said source and an output from the first stage of said shift register to produce said variable-width pulses; said third means includes second gate means coupled to an output from the first stage of said shift register and an output from the second stage of said shift register to produce said constant-width pulses; a constant voltage source; said fourth means includes a capacitor coupled to said first and second gate means and said constant voltage source to produce said control voltage; and said fifth means includes an amplifier coupled to said capacitor to apply said control voltage to said varactor diode.
Claim 10
Dependent Claim
56 words
An arrangement according to claim 8, wherein said first gate means is coupled to the inverting output of the first stage of said shift register; and said second gate means is coupled to the normal output of the first stage of said shift register and the inverting output of the second stage of said shift register.
Claim 11
Dependent Claim
79 words
An arrangement according to claim 9, wherein said first gating means includes a first NAND gate coupled to said source and the inverting output of the first stage of said shift register; and said second gating includes a second NAND gate coupled to the normal output of the first stage of said shift register and the inverting output of the second stage of said shift register, and a NOT gate coupled to the output of said second NAND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-12 | 1975-01-11 | 1975-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-12 | 1979-01-11 | 1979-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-12 | 1983-01-11 | 1983-07-13 | $7700.00 | Window Closed / Lapsed |