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US3591852A
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Nonvolatile field effect transistor counter
Assignee: General Electric Co
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Filing: 1969-01-21
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Granted: 1971-07-06
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Expires: 1989-01-21
Abstract
Abstract Conductor-insulator semiconductor field effect transistors characterized by a nonuniform charge in the insulator under a large voltage bias at room temperatures are employed as nonvolatile counters wherein the count per stage is controlled by the amplitude and/or pulse width of large voltage count pulses applied to the transistor. The charge switching characteristic produces a generally cumulative time-voltage shift in the transistor transfer characteristic and the transistor switches from a substantially nonconductive state to a stable conductive state after a predetermined number of count pulses have effected a shift in the transfer characteristic to a constantly applied DC bias. The transistor then can be reset to a different switching count for identical applied count pulses by a variation in the amplitude and/or period of the reset voltage applied to the transistor gate electrode. Preferably the transistors are cascaded to produce a nonvolatile, highly accurate counter having a minimum number of semiconductive devices per stage.
Inventors
- 👤 Arthur C M Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:55
CPC Classifications
H; H03; H03K; H03K25/00; H10; H10D; H10D99/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
29 words
A nonvolatile counter according to claim 1 including means for applying a reset voltage pulse to said gate electrode in a polarity opposite the polarity of said count pulses.
Claim 2
Dependent Claim
36 words
A nonvolatile counter according to claim 2 further including means for controlling the waveform of said reset pulse to alter the number of count pulses required to effect an alteration in the conductivity of said transistor.
Claim 3
Dependent Claim
26 words
A nonvolatile counter according to claim 1 wherein said semiconductor is silicon and at least a portion of said insulator includes a zone of silicon nitride.
Claim 4
Dependent Claim
57 words
A nonvolatile counter according to claim 4 wherein said field effect transistor is formed of a silicon wafer having source and drain regions diffused therein, a silicon dioxide layer overlying said silicon wafer intermediate said source and drain electrodes, a silicon nitride layer overlying said silicon dioxide layer and a metal electrode overlying said silicon nitride layer.
Claim 5
Dependent Claim
34 words
A nonvolatile counter according to claim 5 including means for applying a voltage to said silicon wafer to reduce the amplitude of the count pulses required to shift the transfer characteristic of said transistor.
Claim 6
Dependent Claim
168 words
A nonvolatile counter comprising a plurality of conductor-insulator-semiconductor field effect transistors having source, drain and gate electrodes therein, each of said transistors being characterized by a nonuniform stored charge distribution in the insulator under a large voltage bias, said source and drain electrodes of said transistors being respectively connected to common sources of potential, count means connected to the gate electrode of each transistor, said pulses from said count means effecting a shift in the transfer characteristic of said transistor by a predetermined amount upon application thereto, first switching means disposed between said count means and the gate electrodes of each of said plurality of transistors for blocking pulses from said count means to the gate electrode of each transistor dependent upon the state of conduction of the transistor, and second switching means interconnecting each of said transistors with an adjacent transistor for applying pulses from said count means to the gate electrode of each transistor only upon a switching in the conductive state of said interconnected transistor.
Claim 7
Dependent Claim
45 words
A nonvolatile counter according to claim 7 wherein said semiconductor is silicon and further including means for applying an enabling pulse to the silicon semiconductor to reduce the amplitude of the pulse from said count means required to switch the conductive state of said transistor.
Claim 8
Dependent Claim
40 words
A nonvolatile counter according to claim 7 including reset means connected to the gate electrode of each transistor for applying a pulse to said gate electrodes in a polarity opposite the polarity of the applied pulsEs from said count means.
Claim 9
Dependent Claim
50 words
A nonvolatile counter according to claim 9 including means for controlling the amplitude and period of said reset pulses to vary the number of pulses of a predetermined magnitude and duration from said count means required to shift the transfer characteristic from an original position to a preselected bias voltage.
Claim 10
Dependent Claim
42 words
A nonvolatile counter according to claim 7 including means for varying the pulse width of the waveform from said count means to alter the number of pulses required to shift the transfer characteristic from an original position to a preselected bias voltage.
Claim 11
Dependent Claim
74 words
A nonvolatile counter according to claim 7 wherein said first switching means are insulated gate field effect transistors serially connected between said count means and the gate electrode of said conductor-insulator-semiconductor field effect transistors and further including means for applying an enabling voltage to the semiconductor substrate of said conductor-insulator-semiconductor field effect transistors to reduce the magnitude of the applied pulse from said count means required to shift the transfer characteristic of said transistors.
Claim 12
Dependent Claim
153 words
A counter comprising a transistor having a semiconductive wafer exhibiting a first type electrical conductivity, source and drain electrodes of a second type conductivity diffused into said wafer at spaced apart coplanar locations to provide an area of first type conductivity separating said electrodes, a leaky dielectric with traps overlying said area intermediate said source and drain electrodes, a conductive electrode overlying said dielectric, said transistor being characterized by a nonuniform charge distribution in the insulator under a large voltage bias, means for applying a first voltage to said conductive electrode of a magnitude insufficient to exceed the threshold voltage required to shift the transfer characteristic of said transistor and means for applying a second voltage to said first type conductivity region, said second voltage being cumulative with said first voltage pulse to shift the transfer characteristic of said transistor upon the simultaneous application of said first and second voltages to said transistor.
Claim 13
Dependent Claim
20 words
A counter according to claim 13 wherein said dielectric is formed of juxtaposed layers of silicon nitride and silicon dioxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-05 | 1975-01-04 | 1975-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-05 | 1979-01-04 | 1979-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-05 | 1983-01-04 | 1983-07-06 | $7700.00 | Window Closed / Lapsed |