Machine tool control system

Claim 2

An electrical control system including servo means for relatively positioning a pair of relatively movable members comprising: input means for receiving input information, the information including a feed rate word; an interpolator providing output signals in response to input information provided by said input means, said interpolator including an adder and an accumulator capable of holding interpolator function words; and circuit means coupled to said interpolator and being responsive to said input means for modifying the overflow time for the adder and thereby, the value of the interpolator function words inversely proportional to the value of the feed rate word.

Claim 3

The control system as defined in claim 1 wherein said circuit means includes register means responsive to said feed rate word for registering the value thereof and means for scaling the function words relative to the feed rate word coupled to said interpolator.

Claim 4

The control system as defined in claim 2, wherein said circuit means includes logic circuitry responsive to the contents of said registering means and the feed rate word for readjusting the value of digital pulses which are supplied by said interpolator.

Claim 5

The control system as defined in claim 1 wherein: said interpolator further includes an integrand register coupled to said adder; said circuit means includes means responsive to said feed rate word for registering the value thereof; and means for scaling the function word from the accumulator register relative to the value of the word entered into the integrand register.

Claim 6

A digital computing apparatus comprising: a first means for storing digital information of a predetermined word length; a second means for storing digital information of a changeable word length; adding means for serially adding the contents stored in said first means to the contents of said second means and having an output circuit coupled to said second means for returning the summation thereof to said second means; and logical circuit means for varying the overflow time in the output circuit of said adding means and thereby, the word length value of said second means, said logical circuit means being responsive to the digital weight of the digital word of information stored in said first means.

Claim 7

A digital computing apparatus comprising: a first means for storing digital information of a predetermined word length; a second means for storing digital information of a changeable word length; adding means for serially adding the contents stored in said first means to the contents of said second means and having an output circuit coupled to said second means for returning the summation thereof to said second means; and logical circuit means for varying the overflow time in the output circuit of said adding means and thereby, the word length value of said second means, said logical circuit means being responsive to the digital weight of the digital word of information stored in said first means.

Claim 8

The apparatus as defined in claim 5, said logical circuit means comprising gating means coupled to the output circuit of said adding means for supplying output increments when the storage of said second means reaches an overflow capacity.

Claim 9

The apparatus as defined in claim 5, said logical circuit means comprising: a register, said register having an input circuit being coupled to said first means and being capable of registering the weight of the digital input word, said register having an output circuit being coupled to said adding means for varying overflow time of the adding means and thereby the capacity of said second means; and gating means, coupled to the output of said adding means, for supplying output increments when the accumulations in said second means reaches an overflow capacity and further being responsive to a predetermined condition of said digital counter.

Claim 10

The apparatus as defined in claim 5 wherein: said first means includes an integrand register having an input circuit being capable of receiving a digital integrand word and an output circuit; said second means includes an accumulation register having an input circuit being capable of receiving the summation of said adding means; and said logical circuit means comprising a register, said latter register having an input circuit being coupled to the input circuit of the integrand register of said first means and being capable of registering the weight of the digital input word, said latter register having an output circuiT being coupled to the output circuit of said adding means for varying the overflow time of the adding means and thereby the capacity of said second means.

Claim 11

The apparatus as defined in claim 5 wherein said first means includes an integrand register, said integrand register having an input circuit being capable of receiving a digital integrand word and an output circuit, the output circuit being coupled to said adding means, and said second means including an accumulator register, said accumulator register having an input circuit being capable of receiving the summation of said adding means, said logical circuit means comprising: a marker register capable of registering the weight of the digital input word received by the integrand register of said first means, said marker register having an input circuit coupled to the input circuit of the integrand register of said first means.

Claim 12

The apparatus as defined in claim 5 wherein said first means includes an integrand register, said integrand register having an input circuit being capable of receiving a digital integrand word and an output circuit, the output circuit being coupled to said adding means, and said second means including an accumulator register, said accumulator register having an input circuit being capable of receiving the summation of said adding means, said logical circuit means comprising: a digital counter and marker register, said marker register being capable of registering the weight of the digital input word received by the integrand register of said first means, said marker register having an input circuit coupled to the input circuit of the integrand register of said first means and having an output circuit; and gating means coupled to the output circuit of said adding means for supplying output increments when the accumulations in the accumulator register of said second means reaches an overflow capacity, said gating means being further responsive to a predetermined condition of said digital counter.

Claim 13

A digital computing integrator comprising: an integrand register, said integrand register having an input circuit for receiving digital data words of a predetermined word length and an output circuit; a serial adder, said serial adder having a first input circuit, a second input circuit and an output circuit, the first input circuit of said serial adder being coupled to the output circuit of said integrand register; an accumulator register, said accumulator register having an input circuit and an output circuit, the input circuit of said accumulator register being coupled to the output circuit of said serial adder and the output circuit of said accumulator register being coupled to the second input circuit of said serial adder, said accumulator register having a variable word length capacity; and logical means coupled to the output circuit of said adder for varying the overflow time at the output circuit of the adder and thereby the capacity of said accumulator register, said means being coupled to said accumulator register and being responsive to the length of the word to be stored in said integrand register.

Claim 14

A digital computing integrator comprising: an integrand register, said integrand register having an input circuit for receiving digital data words of a predetermined word length and an output circuit; a serial adder, said serial adder having a first input circuit, a second input circuit and an output circuit, the first input circuit of said serial adder being coupled to the output circuit of said integrand register; an accumulator register, said accumulator register having an input circuit and an output circuit, the input circuit of said accumulator register being coupled to the output circuit of said serial adder and the output circuit of said accumulator register being coupled to the second input circuit of said serial adder, said accumulator register having a variable word length capacity; and logical means coupled to the output circuit of said adder for varying the overflow time at the output circuit of the adder and thereby the capacity of said accumulator register, said means being coupled to said accumulator register and being responsive to the length of the word to be stored in said integrand register.

Claim 15

The integrator as defined in claim 11 wherein said logical means comprises a marker register and a digital counter, said marker register having an input circuit and an output circuit, the input circuit of said marker register being coupled to the input of said integrand register and the output of said marker register being coupled to said adder for varying the overflow time in the output of said adder and thereby the capacity of said accumulator register.

Claim 16

The integrator as defined in claim 11, said logical means comprising gating mean coupled to the output circuit of said adder and being responsive to predetermined conditions of the input word and overflow increments from said accumulator.

Claim 17

The integrator as defined in claim 11, wherein said logical means comprises: means including a digital counter, said latter means having an input circuit being coupled to the input circuit of said integrand register and being responsive to register weight of the digital data words thereof, and an output circuit being coupled to said logical means for varying the overflow time and thereby the capacity of said accumulator register; and gating means coupled to the output circuit of said adder and being responsive to predetermined conditions of said digital counter for gating overflow increments in the output circuit of the adder.

Claim 18

In a control system having servo means for relatively positioning a pair of relatively movable members comprising: input means for receiving at least a pair of digital words, one of which includes a feed rate number; a digital integrator, said integrator including: an integrand register, said integrand register having an input circuit coupled to said input means and an output circuit, an accumulator, said accumulator having an input circuit and an output circuit and an adder, said adder having a pair of input circuits and an output circuit, one of the pair of adder input circuits being coupled to the output circuit of the integrand register and the other adder input circuit being coupled to the output circuit of the accumulator register, the output circuit of the adder being coupled to the input circuit of the accumulator register, said integrator being coupled to receive the digital words on the input of integrand register; logical means coupled to the integrand input circuit of said integrator for determining the value of the feed rate number; and gating means responsive to said means for determining the value of the feed rate number for gating overflow in the output of the adder and thereby adjusting the accumulator capacity of said integrator inversely proportional to the value of the feed rate number.

Claim 19

In a control system having servo means for relatively positioning a pair of relatively movable members comprising: input means for receiving at least a pair of digital words, one of which includes a feed rate number; a digital integrator, said integrator including: an integrand register, said integrand register having an input circuit coupled to said input means and an output circuit, an accumulator, said accumulator having an input circuit and an output circuit and an adder, said adder having a pair of input circuits and an output circuit, one of the pair of adder input circuits being coupled to the output circuit of the integrand register and the other adder input circuit being coupled to the output circuit of the accumulator register, the output circuit of the adder being coupled to the input circuit of the accumulator register, said integrator being coupled to receive the digital words on the input of integrand register; logical means coupled to the integrand input circuit of said integrator for determining the value of the feed rate number; and gating means responsive to said means for determining the value of the feed rate number for gating overflow in the output of the adder and thereby adjusting the accumulator capacity of said integrator inversely proportional to the value of the feed rate number.

Claim 20

In a machine tool control system for use in contour cutting employing first and second digital integrators to perform interpolation functions to control machine axes; a buffer register capable of holding a plurality of words for imparting machine tool axes movement and including a feed rate number to determine the rate of feed in which the machine tool moves; a free-running digit counter operating in synchronism with said buffer storage; a marker register for storing the most significant bit of the feed rate number from said buffer storage and being incremented in synchronism with said digital counter; first control logic means coupled to said marker register and said interpolator for determining the interpolation overflow therefrom; a scaling register for controlling interpolation overflow inversely proportional to said marker register for incrementing the second interpolator in said system; and second control logic means coupled to said interpolators to cause incrementations therefrom at predetermined times depending upon the axis word from said buffer storage.

Claim 21

In a machine tool control system for use in contour cutting employing first and second digital integrators to perform interpolation functions to control machine axes; a buffer register capable of holding a plurality of words for imparting machine tool axes movement and including a feed rate number to determine the rate of feed in which the machine tool moves; a free-running digit counter operating in synchronism with said buffer storage; a marker register for storing the most significant bit of the feed rate number from said buffer storage and being incremented in synchronism with said digital counter; first control logic means coupled to said marker register and said interpolator for determining the interpolation overflow therefrom; a scaling register for controlling interpolation overflow inversely proportional to said marker register for incrementing the second interpolator in said system; and second control logic means coupled to said interpolators to cause incrementations therefrom at predetermined times depending upon the axis word from said buffer storage.

Claim 22

The system as defined in claim 16 and further comprising: a distance-to-go register, said distance-to-go register being coupled to said buffer register and capable of receiving the appropriate axes movement number therein; and said second control logic means coupled to said distance-to-go register and being incremented by the interpolators of said system for incrementally subtracting the value of the axes movement in said distance-to-go counter in relation to the interpolator function.

Claim 23

The system as defined in claim 16 and further comprising: command pulse generators; and logic means coupled to said buffer storage register and being responsive to said command pulse generators for transferring the data in said buffer storage to said distance-to-go register at predetermined times.

Claim 24

The system as defined in claim 16 and further comprising; logic means coupled to said digit counter and said marker register for enabling the control logic to enable a predetermined interpolator of said system.

Claim 25

The machine tool conTrol system as defined in claim 17 and further including; logic gating means coupled to said buffer register for gating preselected buffer words to a selected interpolator.

Claim 26

The system as defined in claim 17 and further comprising: a distance-to-go register, said distance-to-go register being coupled to said buffer register and capable of receiving the appropriate axes movement number therein; logic means coupled to said distance-to-go register and being incremented by the interpolators of said system for incrementally subtracting the value of the axes movement in said distance-to-go counter in relation to the interpolator function; and logic gating means coupled to said buffer register for gating preselected buffer words to a selected interpolator.

Claim 27

The system as defined in claim 17 and further comprising: command pulse generators; a first logic means coupled to said buffer storage register and being responsive to said command pulse generators for transferring the date in said buffer storage to said distance-to-go register at predetermined times; and a second logic means coupled to said digit counter and said marker register for enabling said control logic to enable a predetermined interpolator of said system.

Claim 28

An electrical system having servo means for relatively positioning a pair of relatively movable members, comprising: discrete signal program means for producing feed rate signals and for producing distance-to-go signals; first integrator means having an output and having an input for receiving said feed rate signals; second integrator means having an output and having an input for receiving said distance-to-go signals, said second integrator means being controlled by said first integrator means to cause distance-to-go signals to be produced at the output of said second integrator means for controlling said servo means; and circuit means having an input for receiving said feed rate signals, and having output circuits coupled to both of said integrator means, said circuit means being responsive to said feed rate signals for increasing the frequency of signals at the output of one of said integrator means while decreasing the frequency of signals at the output of the other integrator means.

Claim 29

An electrical system having servo means for relatively positioning a pair of relatively movable members, comprising: discrete signal program means for producing feed rate signals and for producing distance-to-go signals; first integrator means having an output and having an input for receiving said feed rate signals; second integrator means having an output and having an input for receiving said distance-to-go signals, said second integrator means being controlled by said first integrator means to cause distance-to-go signals to be produced at the output of said second integrator means for controlling said servo means; and circuit means having an input for receiving said feed rate signals, and having output circuits coupled to both of said integrator means, said circuit means being responsive to said feed rate signals for increasing the frequency of signals at the output of one of said integrator means while decreasing the frequency of signals at the output of the other integrator means.

Claim 30

The electrical system according to claim 23 in which said circuit means comprises: register means including a feed rate register for receiving said feed rate signals; a counter driven at a constant pulse rate; and means for comparing the output of said counter with the output of said register means for controlling the frequency of output of said first integrator means.

Claim 31

The electrical system according to claim 24 in which said register means includes additionally: a scaling register responsive to said feed rate register; and means for comparing the output of said counter with the output of said scaling register for controlling the frequency of output of said second integrator means.

Claim 32

The electrical system according to claim 23 in which said first integrator means and said second integrator means each comprise: an integrand register for receiving either said feed rate signals or said distance-to-go signals; an accumulator register; and an adder coupled to said integrand register and to said accumulator register for adding the contents of said integrand register to the contents of said accumulator register.

Claim 33

The electrical system according to claim 26, including: variable frequency generator means coupled to said adder of said first integrator means for controlling the rate in said first integrator means at which the contents of said integrand register are combined with the contents of said accumulator register; and a switching circuit coupling the output of said first integrator means to said adder of said second integrating means for controlling the rate in said second integrator means at which the contents of said integrand register arE combined with the contents of said accumulator register.

Claim 34

The electrical system according to claim 27, including: a distance-to-go register for receiving said distance-to-go signals; and means coupled to the output of said second integrator means and coupled to said distance-to-go register for generating a stop signal when the output of said second integrator bears a predetermined relationship to the distance-to-go.