Variable delay circuit

Abstract

Abstract AN AUTOMATIC VARIABLE DIGITAL DELAY CIRCUIT TO COMPENSATE A DIGITAL SIGNAL FOR VARIABLE DELAYS IN NETWORKS EMPLOYING TDM CHANNELS. THE CIRCUIT INCLUDES A FIRST SHIFT REGISTER IN WHICH THE SYNC PULSE OF THE INPUT PULSE TRAIN IS STEPPED THERETHROUGH AT A GIVEN RATE. THE OUTPUT OF EACH SHIFT REGISTER STAGE IS GATED WITH A LOCAL SYNC PULSE. THE STAGE THAT IS "ON" WHEN LOCAL SYNC PULSE OCCURS IDENTIFIES THE DELAY NECESSARY TO ACHIEVE SYNC. THIS DELAY IS OBTAINED BY PASSING THE ENTIRE PULSE TRAIN THROUGH A SECOND IDENTICAL SHIFT REGISTER AND TAK- ING THE OUTPUT FROM THE STAGE THEREOF CORRESPONDING TO THE STAGE OF THE FIRST SHIFT REGISTER IDENTIFYING REQUIRED DELAY.

Inventors

• 👤 Roger Alan Manship

Bibliographic Details