Memory arrangement having both magnetic-core and switching-device storage with a common address register

Claim 1

A memory arrangement organized with a plurality of words and a given number of bit positions per word, comprising: a first memory section having a plurality of magnetic cores each having a given one of said bit positions, a plurality of memory drivers, a plurality of memory switches, a plurality of word wires each connected from a memory driver through some of said cores to a memory switch, a plurality of sense windings each individual to one of said bit positions and coupled to at least one of the cores thereof; a second memory section having a plurality of sets of bistable devices, each having an individual output with one of two potential conditions selectively thereon according to the state of the device, each set storing one word and each device of a set being for 1 bit position, individual gates connected to said outputs; memory address means using a numbering system having a first and a second part for each address with first and second groups of address conductors for the two parts respectively, the memory drivers being connected to conductors of the first group and the memory switches being connected to conductors of the second group; each said set of the second memory section having gate enabling means coupled to conductors of the first and second groups of address conductors and to the gates of the set; memory output means coupling said sense windings and said gates to inputs for respective bit positions of at least one output register; the arrangement being operative responsive to selection of an address of the first section to actuate from the address means at least one driver via conductors of the first group and at least one switch via conductors of the second group to produce current flow through the word wire connected to that driver and switch, which selectively induces potentials in sense windings of cores threaded by the word wire in accordance with the information stored in that word, and the memory output means responding to the sense winding potentials to store the information in at least one output register; and alternatively the arrangement being operative responsive to selection of an address of the second section to actuate from the address means the gate enabling means for that word via conductors of the first and second groups, which enables the gates of that set to cause the memory output means to respond to the potentials at the device outputs to store the information in at least one output register; the improvement wherein said gate enabling means for each set of the second memory section comprises a transformer having a primary and a secondary winding, and coupling means between the secondary winding and the gates of that set, with the primary winding connected between one of said memory drivers and one of said memory switches whereby current flows therein responsive to selection of the corresponding address similar to the current flow in a word wire of the first section, the current flow in the primary winding including a potential in the secondary winding to actuate said coupling means, which enables the gates.