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US3586884A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit to control the duration of pulses

Assignee: International Standard Electric Corp
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Filing: 1968-12-23
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Granted: 1971-06-22
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Expires: 1988-12-23
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Abstract

Abstract The duration of pulses may be controlled to have a given constant width, or a variable width to convey intelligence by the circuit of this invention. A semiconductor device receives a pulse input whose width is to be maintained constant or varied. A bias voltage, constant or variable, is coupled to the control electrode of said device to adjust the storage time thereof. The output of said device and the pulse input are coupled to an OR gate to produce either said constant or variable width pulse output. Negative feedback to the control electrode may be employed to compensate the pulse output for temperature variations.

Inventors

  • 👤 Gerhard Gunter Gassmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 11:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/05; H03K19/00; H03K19/02; H03K19/12; H03K3/00; H03K3/02; H03K3/33; H03K7/00; H03K7/08

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 89 words
A circuit to control the duration of pulses comprising: a first source of input pulses; a semiconductor device having at least an output electrode and a control electrode, said control electrode being coupled to said first source; a second source of control voltage coupled to said control electrode to control the storage time of said device; and a combining circuit coupled to said output electrode and said first source to combine said input pulse and an output pulse at said output electrode to provide output pluses of controlled duration.
Claim 2
Dependent Claim 89 words
A circuit to control the duration of pulses comprising: a first source of input pulses; a semiconductor device having at least an output electrode and a control electrode, said control electrode being coupled to said first source; a second source of control voltage coupled to said control electrode to control the storage time of said device; and a combining circuit coupled to said output electrode and said first source to combine said input pulse and an output pulse at said output electrode to provide output pluses of controlled duration.
Claim 3
Dependent Claim 18 words
A circuit according to claim 1, wherein said second source provides a fixed value for said control voltage.
Claim 4
Dependent Claim 18 words
A circuit according to claim 1, wherein said second source provides a variable value for said control voltage.
Claim 5
Dependent Claim 13 words
A circuit according to claim 3, wherein said variable value includes intelligence signals.
Claim 6
Dependent Claim 31 words
A circuit according to claim 1, wherein said device includes a transistor having its base electrode coupled to said first and second sources and its collector coupled to said combining circuit.
Claim 7
Dependent Claim 14 words
A circuit according to claim 1, wherein said combining circuit includes an OR gate.
Claim 8
Dependent Claim 32 words
A circuit according to claim 1, further including a negative feedback circuit coupled between the output of said combining circuit and said control electrode to compensate said output pulses for temperature variations.
Claim 9
Dependent Claim 51 words
A circuit according to claim 1, wherein said second source provides a fixed value for said control voltage; said combining circuit includes an OR gate; and said device includes a transistor having its base electrode coupled to said first and second sources and its collector electrode coupled to said OR gate.
Claim 10
Dependent Claim 50 words
A circuit according to claim 1, wherein said second source provides intelligence signals for said control voltage; said combining circuit includes an OR gate; and said device includes a transistor having its base electrode coupled to said first and second sources and its collector electrode coupled to said OR gate.
Claim 11
Dependent Claim 76 words
A circuit according to claim 1, wherein said second provides intelligence signals for said control electrode; said combining circuit includes an OR gate; and said device includes a transistor having its base electrode coupled to said first and second sources and its collector electrode coupled to said OR gate; and further including a negative feedback circuit coupled between the output of said OR gate and said base electrode to compensate said output pulses for temperature variations.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-06-21 1974-12-21 1975-06-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-06-21 1978-12-21 1979-06-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-06-21 1982-12-21 1983-06-22 $7700.00 Window Closed / Lapsed

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