Patent US3586878A successfully refreshed from Google Patents.
US3586878A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample,integrate and hold circuit
Assignee: Collins Radio Co
•
Filing: 1969-03-17
•
Granted: 1971-06-22
•
Expires: 1989-03-17
Abstract
Abstract A signal sample, integrate, and hold circuit with data signal samples AND enabled to generally insure that when a signal is coexistent with the enable signal only a portion of the data bit truly predictably present in certain data bit cycle periods is passed to an integrating circuit with charging of a capacitor thereby to and through a triggering circuit threshold voltage actuating level. The triggering circuit in turn along with a clock signal actuates a flip-flop circuit providing data output one period delayed from data timing system referenced.
Inventors
- 👤 Kenneth Y Maxham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:45
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H04; H04L; H04L25/00; H04L25/02; H04L25/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
190 words
In a data signal sample, integrate, and hold circuit for enhancing the detection of out-of-phase digital data: digital data signal input circuit means; clock timing signal generating means having a clock signal output, an enable signal output, and a reset signal output all in data bit frequency sequenced and synchronized relation; an AND gate circuit having input connections from said input circuit means and the enable signal output; signal integrating circuit means with energy accumulating capacitive means, with a charge through a signal level capability, connected to receive an input from the output of said AND gate circuit; a threshold activated change of state circuit connected to the output of said signal integrating circuit means for developing a detected signal resulting output at output means of said change of state circuit; reset circuit means connected across said energy accumulating capacitive means and connected to receive said reset signal output for repeated discharging of said energy accumulating capacitive means for each data bit operational cycle; and with the clock signal output of said clock timing signal generating means connected as an additional input to said threshold activated change of state circuit.
Claim 2
Dependent Claim
190 words
In a data signal sample, integrate, and hold circuit for enhancing the detection of out-of-phase digital data: digital data signal input circuit means; clock timing signal generating means having a clock signal output, an enable signal output, and a reset signal output all in data bit frequency sequenced and synchronized relation; an AND gate circuit having input connections from said input circuit means and the enable signal output; signal integrating circuit means with energy accumulating capacitive means, with a charge through a signal level capability, connected to receive an input from the output of said AND gate circuit; a threshold activated change of state circuit connected to the output of said signal integrating circuit means for developing a detected signal resulting output at output means of said change of state circuit; reset circuit means connected across said energy accumulating capacitive means and connected to receive said reset signal output for repeated discharging of said energy accumulating capacitive means for each data bit operational cycle; and with the clock signal output of said clock timing signal generating means connected as an additional input to said threshold activated change of state circuit.
Claim 3
Dependent Claim
106 words
The data signal sample, integrate, and hold circuit of claim 1 wherein, said signal integrating circuit means includes a transistor circuit connected between a DC voltage supply and a voltage potential reference source with activation to completing a charging circuit path for said energy accumulating capacitive means upon receiving an activating input from said AND gate circuit; and said reset circuit means connected across said energy accumulating capacitive means includes a transistor with the emitter and collector electrodes in the reset discharge circuit path for said capacitive means, and the transistor base connected for receiving the reset signal output of said clock timing signal generating means.
Claim 4
Dependent Claim
29 words
The data signal sample, integrate, and hold circuit of claim 2 wherein, said clock timing signal generating means includes enable pulse delayed signal circuit means for leading only signals.
Claim 5
Dependent Claim
29 words
The data signal sample, integrate, and hold circuit of claim 2 wherein, said clock timing signal generating means includes enable pulse delayed signal circuit means for lagging only signals.
Claim 6
Dependent Claim
59 words
The data signal sample, integrate, and hold circuit of claim 2 wherein, said clock timing signal generating means includes two enable pulse delayed signal subcircuits, the first a leading only data signal enable circuit, and the second a lagging only data signal enable circuit; and switch means for switching between leading only and lagging only signal modes of operation.
Claim 7
Dependent Claim
47 words
The data signal sample, integrate, and hold circuit of claim 5 wherein, both the leading only and lagging only data signal enable subcircuits are connected to a lead-and-lag enable signal developing subcircuit; and with said switch means also selectively switchable tO the lead-and-lag enable signal developing subcircuit.
Claim 8
Dependent Claim
33 words
The data signal sample, integrate, and hold circuit of claim 2 wherein, a threshold signal actuated first trigger circuit is included in the signal path of said digital data signal input circuit means.
Claim 9
Dependent Claim
34 words
The data signal sample integrate, and hold circuit of claim 7 wherein, a threshold signal actuated second trigger circuit is included in the circuit signal path to said threshold activated change of state circuit.
Claim 10
Dependent Claim
25 words
The data signal sample, integrate, and hold circuit of claim 8 wherein, said threshold activated change of state circuit is a set-reset trigger flip-flop circuit.
Claim 11
Dependent Claim
56 words
The data signal sample, integrate, and hold circuit of claim 2 wherein, said transistor circuit includes a transistor with the emitter and collector electrodes in the DC voltage supply to voltage potential reference charging path for said capacitive means, and the transistor base is connected for transistor saturation with signal output from said AND gate circuit.
Claim 12
Dependent Claim
67 words
The data signal sample, integrate, and hold circuit of claim 10 wherein, an additional transistor is provided with a base connection to the output of said AND gate circuit, an emitter connection to said voltage potential reference source, and a collector circuit connection through resistive means to said DC voltage supply and also to the base of the transistor in the charging path for said capacitive means.
Claim 13
Dependent Claim
64 words
The data signal sample, integrate, and hold circuit of claim 4 wherein, said DC voltage supply is a positive voltage supply; said voltage potential reference source is ground; said transistor in the charging path for said capacitive means is a PNP transistor with the emitter connected to the positive voltage supply; and the two other transistors are NPN transistors with emitters connected to ground.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-21 | 1974-12-21 | 1975-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-21 | 1978-12-21 | 1979-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-21 | 1982-12-21 | 1983-06-22 | $7700.00 | Window Closed / Lapsed |