Pulse summarizer circuit comprising plural capacitors and single constant current discharge means for pulse data on plural input channels

Claim 2

In combination, a plurality of capacitor, each being individually chargeable to a predetermined voltage in response to random input pulses, and a discharge circuit connected in common to each of said capacitors and responsive to a charging of any combination of said capacitors for producing a linear ramp signal for each one of said capacitors charged.

Claim 3

The combination in accordance with claim 1 wherein said discharge circuit comprises a constant current transistor arrangement and a plurality of diodes each of which couples an individual one of said capacitors to said transistor arrangement.

Claim 4

The combination in accordance with claim 2 wherein said transistor arrangement includes a single transistor having base, emitter and collector electrodes, biasing means comprising a Zener diode electrically connected to said diodes and responsive to a charging of any one of said capacitors for establishing a regulated emitter base bias for said transistor, and said transistor being responsive to said regulated bias for supplying a variable impedance in a discharge path for said one capacitor to produce a constant discharge current for said one capacitor and a linear negative ramp signal.

Claim 5

The combination in accordance with claim 3 further comprising amplifier means serially connected between said diodes and said biasing means for producing an output linear negative ramp signal, said latter signal being applied to said Zener diode for establishing said regulated emitter base bias for said transistor.

Claim 6

The combination in accordance with claim 3 further comprising resistance means serially connected with said diodes and said transistor for controlling the duration of said ramp signal.

Claim 7

The combination in accordance with claim 5 wherein said transistor is controlled by said resistance means and a charging off only one of said capacitors for producing a linear negative ramp signal of a predetermined duration.

Claim 8

The combination in accordance with claim 6 wherein said transistor is controlled by said resistance means and a concurrent charge of a plurality of said capacitors for producing negative ramp signals of other durations in response to input pulses overlapping in time.

Claim 9

The combination in accordance with claim 3 further comprising a plurality of capacitor charging circuits, each of said circuits electrically connected to an individual one of said capacitors for charging said one capacitor to a regulated voltage for a predetermined time duration.

Claim 10

The combination in accordance with claim 8 wherein each of said capacitor charging circuits comprises a pulse converter responsive to a receipt of an input pulse for converting said pulse into an output pulse of a regulated voltage and fixed time duration for charging a respective individual one of said capacitors.

Claim 11

A circuit for summarizing random pulses received over a plurality of channels and comprising a plurality of pulse converters, each of said converters being associated with an individual one of said channels for converting a pulse thereon into a regulated output voltage of a prescribed duration, a plurality of capacitors, each one of said capacitors being connected to an individual one of said converters for charging said one capacitor to said regulated converter voltage, an arrangement common to each of said capacitors for discharging each charged one of said capacitors to produce ramp signals for each said charged one of said capacitors, and means responsive to each of said ramp signals for generating output pulses equal in number to pulses received over said channels.

Claim 12

A circuit for summarizing random pulses received over a plurality of channels and comprising a plurality of pulse converters, each of said converters being associated with an individual one of said channels for converting a pulse thereon into a regulated output voltage of a prescribed duration, a plurality of capacitors, each one of said capacitors being connected to an individual one of said converters for charging said one capacitor to said regulated converter voltage, an arrangement common to each of said capacitors for discharging each charged one of said capacitors to produce ramp signals for each said charged one of said capacitors, and means responsive to each of said ramp signals for generating output pulses equal in number to pulses received over said channels.

Claim 13

A random pulse summarizing circuit in accordance with claim 10 wherein said discharging arrangement comprises a circuit for generating a constant discharge current for said capacitors to produce individual ramp signals for each said charged capacitors, said circuit including a plurality of diodes, each connecting said circuit to an individual one of said capacitors, a transistor having base, emitter and collector electrodes, biasing means comprising a resistor and a Zener diode electrically connected to said diodes and responsive to a charging of any of said capacitors for establishing a regulated emitter base electrode bias for said transistor, said transistor being responsive to said regulated bias for supplying a variable impedance in a discharge path including said emitter and collector electrodes for said capacitors to produce a predetermined constant discharge current for said capacitors and linear ramp signals.

Claim 14

A random pulse summarizing circuit in accordance with claim 11 further comprising resistance means serially connected with said diodes and said emitter electrode for controlling the duration of each of said ramp signals, and wherein said circuit is controlled by said resistance means and a charging of only one of said capacitors for producing a linear negative ramp signal of a predetermined duration, said circuit being further controlled by said resistance means and a concurrent charging of a plurality of said capacitors for producing negative ramp signals of other durations, and said generating means being responSive to said ramp signals of said predetermined and said other durations for generating output pulses with a fixed period.

Claim 15

A random pulse summarizing circuit in accordance with claim 12 further comprising an emitter-follower transistor amplifier serially connected with said diodes and said biasing means for amplifying said negative ramp signals said amplified signals being applied to said Zener diode for establishing said regulated emitter base bias for said transistor.

Claim 16

A random pulse summarizing circuit in accordance with claim 13 wherein said generating means includes a pulse generator and a threshold detector responsive to each of said ramp signals for activating said generator to generate output pulses equal in number to pulses received over said channels, and further comprising an electromechanical register responsive to said output pulses for providing a summary total of the number of pulses received over said channels.

Claim 17

A circuit for actuating a single peg count register in response to the occurrence of pulses on a plurality of channels comprising an individual capacitor for each of said channels, means for applying a predetermined charge to each of said capacitors on occurrence of a pulse on that capacitor''s channel, constant current discharge means for discharging any charged capacitor to produce a linear ramp voltage, the charging of any capacitor initiating another linear ramp voltage and interrupting the discharge of any priorly charged capacitor until both capacitors have discharged equally, and means for applying pulses to the peg count register while the linear ramp voltage is above a predetermined threshold.

Claim 18

A circuit for actuating a single peg count register in response to the occurrence of pulses on a plurality of channels comprising an individual capacitor for each of said channels, means for applying a predetermined charge to each of said capacitors on occurrence of a pulse on that capacitor''s channel, constant current discharge means for discharging any charged capacitor to produce a linear ramp voltage, the charging of any capacitor initiating another linear ramp voltage and interrupting the discharge of any priorly charged capacitor until both capacitors have discharged equally, and means for applying pulses to the peg count register while the linear ramp voltage is above a predetermined threshold.

Claim 19

A circuit in accordance with claim 15 wherein said constant current discharge means includes means for producing a negative linear ramp voltage and wherein said capacitors are connected to said constant current discharge means to change the slope of the linear ramp voltage on simultaneous discharge of a plurality of said capacitors, whereby the duration of discharge is increased.