Binary full adder utilizing operational amplifiers

Claim 2

A digital logic circuit comprising: an adder-comparator stage receiving at least two digital inputs, each of which is weighted by a power of 2 and summed therein, said adder-comparator stage providing a ''''1'''' output when the result of said summation is equal to or larger than the threshold of said adder-comparator stage, where said threshold is set equal to the next higher power of 2; and an adder stage including an operational amplifier receiving the same at least two digital inputs and weighting them by the same power of 2 as used in said adder-comparator stage, said adder stage further receiving the output of said adder-comparator stage and weighting it by an amount equal to the threshold of said adder-comparator stage multiplied by minus 1, and further summing all of said weighted inputs, the output of said adder stage providing an output digit and the output of said addercomparator stage providing a carry digit.

Claim 3

A digital adder circuit for summing two digital numbers each comprising one bit, which comprises: an adder-comparator stage receiving a carry bit from a prior stage and the two bits of said digital numbers, said adder-comparator stage weighting said carry bit and said two bits by 20 and summing said weighted bits to provide a ''''1'''' output when the results of said summation are equal to or larger than the threshold of said adder-comparator stage, where said threshold is set equal to 21, and a ''''0'''' output when the results of said summation are smaller than said threshold; and an adder stage, including an operational amplifier, receiving said carry bit and said two bits, said adder stage weighting said carry bit and said two bits by 2o, said adder stage further receiving the output of said adder-comparator stage and weighting it by a factor of -21, the output of said adder stage providing an output digit and the output of said adder-comparator stage providing a carry digit.

Claim 4

A digital adder circuit for summing two digital numbers each comprising one bit, which comprises: an adder-comparator stage receiving a carry bit from a prior stage and the two bits of said digital numbers, said adder-comparator stage weighting said carry bit and said two bits by 20 and summing said weighted bits to provide a ''''1'''' output when the results of said summation are equal to or larger than the threshold of said adder-comparator stage, where said threshold is set equal to 21, and a ''''0'''' output when the results of said summation are smaller than said threshold; and an adder stage, including an operational amplifier, receiving said carry bit and said two bits, said adder stage weighting said carry bit and said two bits by 2o, said adder stage further receiving the output of said adder-comparator stage and weighting it by a factor of -21, the output of said adder stage providing an output digit and the output of said adder-comparator stage providing a carry digit.

Claim 5

A digital adder circuit for summing two digital numbers each comprising at lEast two bits, said adder circuit comprising: a first adder-comparator stage receiving a carry bit from an adder circuit of lower significance and the four bits of said two digital numbers, said first adder-comparator stage weighting said carry bit and the least significant two bits of said four bits by a factor of 20 and the remaining two bits by a factor of 21 and, further, summing said five weighted bits to produce a ''''1'''' output if the results of said summation are greater than or equal to the threshold of said adder-comparator stage, and to produce a ''''0'''' output if the results of said summation are smaller than said threshold; a first adder stage, including an operational amplifier, receiving said carry bit and said four bits and further receiving the output of said first adder-comparator stage; said first adder stage weighting said carry bit and the least significant two of said four bits by a factor of 20 and said remaining two bits by a factor of 21 and further weighting said output of the adder-comparator stage by a factor of -22, said first adder stage further summing all six of said weighted bits to produce an output; a second adder-comparator stage receiving the output from said first adder stage and providing a ''''1'''' output if the output of said first adder stage is equal to or greater than 21 and a ''''0'''' output if the output of said first adder stage is less than 21; and a second adder stage, including an operational amplifier, receiving the output of said first adder stage and said second adder-comparator stage, said second adder stage weighting the output of said first adder stage by a factor of 20 and the output of said second adder-comparator stage by -21, said second adder stage further summing said weighted inputs, the output of said first adder-comparator stage providing a carry digit, the output of said second adder-comparator stage provides the most significant output bit and the output of said second adder stage provides the least significant output bit of the summation of said two numbers.

Claim 6

A digital adder circuit for summing two digital numbers each comprising at lEast two bits, said adder circuit comprising: a first adder-comparator stage receiving a carry bit from an adder circuit of lower significance and the four bits of said two digital numbers, said first adder-comparator stage weighting said carry bit and the least significant two bits of said four bits by a factor of 20 and the remaining two bits by a factor of 21 and, further, summing said five weighted bits to produce a ''''1'''' output if the results of said summation are greater than or equal to the threshold of said adder-comparator stage, and to produce a ''''0'''' output if the results of said summation are smaller than said threshold; a first adder stage, including an operational amplifier, receiving said carry bit and said four bits and further receiving the output of said first adder-comparator stage; said first adder stage weighting said carry bit and the least significant two of said four bits by a factor of 20 and said remaining two bits by a factor of 21 and further weighting said output of the adder-comparator stage by a factor of -22, said first adder stage further summing all six of said weighted bits to produce an output; a second adder-comparator stage receiving the output from said first adder stage and providing a ''''1'''' output if the output of said first adder stage is equal to or greater than 21 and a ''''0'''' output if the output of said first adder stage is less than 21; and a second adder stage, including an operational amplifier, receiving the output of said first adder stage and said second adder-comparator stage, said second adder stage weighting the output of said first adder stage by a factor of 20 and the output of said second adder-comparator stage by -21, said second adder stage further summing said weighted inputs, the output of said first adder-comparator stage providing a carry digit, the output of said second adder-comparator stage provides the most significant output bit and the output of said second adder stage provides the least significant output bit of the summation of said two numbers.

Claim 7

A digital adder circuit for summing two digital numbers each comprising (n+1) bits, which comprises: an initial logic circuit including an adder-comparator stage having (n+1) pairs of inputs to receive the least two significant bits through the most significant two bits, respectively, said adder-comparator circuit weighting said pairs of bits by factors of 20 through 2n, respectively, and summing all of said weighted bits to provide a ''''1'''' output if the results of said summation exceed or equal the threshold of said adder-comparator stage, where said threshold is set equal to 2n 1, and to provide a ''''0'''' output if the results of said summation are less than said threshold, and an adder stage, including an operational amplifier, receiving the same inputs received by said adder-comparator stage and weighting said inputs by the same powers of 2 as did said adder-comparator stage, said adder stage further receiving the output of said adder-comparator stage and weighting it by a factor of -2n 1, said adder stage further summing all of said weighted inputs to provide an output; n serially connected logic circuits, each logic circuit including an adder stage, including an operational amplifier, and an adder-comparator stage, the input to said adder-comparator stage and one input to said adder stage having a weighting factor of 20 associated therewith, the adder-comparator stage of the first one of said n logic circuits receiving the output from the adder stage of said initial logic circuit and providing a ''''1'''' output when the output from said initial adder stage is equal to or larger than the threshold of said first Adder-comparator stage, where said threshold is set equal to 2n and providing a ''''0'''' output if the output from said initial adder stage is less than said threshold, the adder stage of first one of said n logic circuits receiving the output of said initial adder stage and the output of said first adder-comparator stage and weighting them by factors of 20 and -2n, respectively, the adder-comparator stage of the ith one of said n logic circuits receiving the output of the adder stage of the i+1th one of said n logic circuits and providing a ''''1'''' output when the output of said i+1th adder stage equal to or larger than the threshold of the ith adder-comparator stage, where said threshold is set equal to 2n 1 i and a ''''0'''' output when said output is smaller than the threshold value, the adder stage of said ith one of said n logic circuits receiving the output of said i+1th adder stage and the output of said ith adder-comparator stage and weighting them by a factor of 20 and -2n 1 i, respectively, the output of said initial adder-comparator-stage providing a carry bit, the output of the first adder-comparator stage providing the n+1th output bit, the output of the ith adder-comparator stage providing the i+1th output bit, the output of the adder-comparator stage of the nth one of said n logic circuits providing the second least significant output bit and the adder stage of said nth logic circuit providing the least significant output bit.

Claim 8

A digital adder circuit for summing two digital numbers each comprising (n+1) bits, which comprises: an initial logic circuit including an adder-comparator stage having (n+1) pairs of inputs to receive the least two significant bits through the most significant two bits, respectively, said adder-comparator circuit weighting said pairs of bits by factors of 20 through 2n, respectively, and summing all of said weighted bits to provide a ''''1'''' output if the results of said summation exceed or equal the threshold of said adder-comparator stage, where said threshold is set equal to 2n 1, and to provide a ''''0'''' output if the results of said summation are less than said threshold, and an adder stage, including an operational amplifier, receiving the same inputs received by said adder-comparator stage and weighting said inputs by the same powers of 2 as did said adder-comparator stage, said adder stage further receiving the output of said adder-comparator stage and weighting it by a factor of -2n 1, said adder stage further summing all of said weighted inputs to provide an output; n serially connected logic circuits, each logic circuit including an adder stage, including an operational amplifier, and an adder-comparator stage, the input to said adder-comparator stage and one input to said adder stage having a weighting factor of 20 associated therewith, the adder-comparator stage of the first one of said n logic circuits receiving the output from the adder stage of said initial logic circuit and providing a ''''1'''' output when the output from said initial adder stage is equal to or larger than the threshold of said first Adder-comparator stage, where said threshold is set equal to 2n and providing a ''''0'''' output if the output from said initial adder stage is less than said threshold, the adder stage of first one of said n logic circuits receiving the output of said initial adder stage and the output of said first adder-comparator stage and weighting them by factors of 20 and -2n, respectively, the adder-comparator stage of the ith one of said n logic circuits receiving the output of the adder stage of the i+1th one of said n logic circuits and providing a ''''1'''' output when the output of said i+1th adder stage equal to or larger than the threshold of the ith adder-comparator stage, where said threshold is set equal to 2n 1 i and a ''''0'''' output when said output is smaller than the threshold value, the adder stage of said ith one of said n logic circuits receiving the output of said i+1th adder stage and the output of said ith adder-comparator stage and weighting them by a factor of 20 and -2n 1 i, respectively, the output of said initial adder-comparator-stage providing a carry bit, the output of the first adder-comparator stage providing the n+1th output bit, the output of the ith adder-comparator stage providing the i+1th output bit, the output of the adder-comparator stage of the nth one of said n logic circuits providing the second least significant output bit and the adder stage of said nth logic circuit providing the least significant output bit.

Claim 9

A parallel adder circuit with high-speed carry, for summing two digital numbers each comprising n+1 bits, which comprises: n+1 parallel-connected adder-comparator stages, the first one of said n+1 adder-comparator stages receiving the two least significant digits of said n+1 bits and weighting them by a factor of 20, said first adder-comparator stage further summing said weighted inputs to produce a ''''1'''' output if the results of said summation are equal to or greater than the threshold of said first adder-comparator stage, where said threshold is set equal to 21, and to produce a ''''0'''' output if said summation is less than said threshold, the second one of said n+1 adder-comparator stages receiving said two least significant bits and the two next more significant bits and weighting the pairs of input bits by 20 and 21, respectively, said second adder-comparator stage summing all said weighted inputs to produce a ''''1'''' output when the results of said summation is equal to or greater than the threshold of said adder-comparator stage, where said threshold is set equal to 22, and a ''''0'''' output when the result of said summation is less than said threshold, the ith one of said n+1 adder-comparator stages receiving said two least significant bits through said ith most significant two bits and weighting the pairs of input bits by factors of 20 through 2i, respectively, said ith adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation exceed the threshold of said ith adder-comparator stage, where said threshold is set equal to 2i 1, and to produce a ''''0'''' output if the results of said summation are less than said threshold, the n+1th one of said adder-comparator stages receiving the least significant two bits through the most significant two bits and weighting the pairs of input bits by factors of 20 through 2n, respectively, said n+1th adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation exceed the threshold of said n+1th adder-comparator stage, where said threshold is set equal to 2n 1, and to produce a ''''0'''' output if the results of said summation are less than said threshold; and n+1 parallel-connected adder stages, the first one of said n+1 adder stages receiving the least two significant bits and weighting them by a factor of 20 and further receiving the output of said first adder-comparator stage and weighting it by a factor of -21, said first adder stage summing all of said weighted inputs, the second one of said n+1 adder stages receiving a carry input from said first adder-comparator stage and the two next bits of higher significance and weighting them by factors of 20, and further receiving the output of said second adder-comparator stage and weighting it by a factor of -21, said second adder stage summing all of said weighted inputs, the ith one of said n+1 adder stages receiving a carry input from the i-1th adder-comparator stage and the i+1th most significant two bits and weighting them by a factor of 20 and further receiving the output of said ith adder-comparator stage and weighting it by a factor of -21, said ith adder stage summing all of said weighted inputs, the n+1th one of said adder stages receiving the carry input from said nth adder-comparator stage and the n+1th two most significant bits and weighting them by a factor of 20, and further receiving the output of said n+1th adder-comparator stage and weighting it by a factor of -21, said n+1th adder stage summing all of said weighted inputs; and the output of said first adder stage providing the least significant output digit, the output of the ith adder stage providing the ith most significant output digit, the output of the n+1th adder stage providing the n+1th most significant output digit and the output of said n+1th adder-comparator stage provides a carry output.

Claim 10

A parallel adder circuit with high-speed carry, for summing two digital numbers each comprising n+1 bits, which comprises: n+1 parallel-connected adder-comparator stages, the first one of said n+1 adder-comparator stages receiving the two least significant digits of said n+1 bits and weighting them by a factor of 20, said first adder-comparator stage further summing said weighted inputs to produce a ''''1'''' output if the results of said summation are equal to or greater than the threshold of said first adder-comparator stage, where said threshold is set equal to 21, and to produce a ''''0'''' output if said summation is less than said threshold, the second one of said n+1 adder-comparator stages receiving said two least significant bits and the two next more significant bits and weighting the pairs of input bits by 20 and 21, respectively, said second adder-comparator stage summing all said weighted inputs to produce a ''''1'''' output when the results of said summation is equal to or greater than the threshold of said adder-comparator stage, where said threshold is set equal to 22, and a ''''0'''' output when the result of said summation is less than said threshold, the ith one of said n+1 adder-comparator stages receiving said two least significant bits through said ith most significant two bits and weighting the pairs of input bits by factors of 20 through 2i, respectively, said ith adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation exceed the threshold of said ith adder-comparator stage, where said threshold is set equal to 2i 1, and to produce a ''''0'''' output if the results of said summation are less than said threshold, the n+1th one of said adder-comparator stages receiving the least significant two bits through the most significant two bits and weighting the pairs of input bits by factors of 20 through 2n, respectively, said n+1th adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation exceed the threshold of said n+1th adder-comparator stage, where said threshold is set equal to 2n 1, and to produce a ''''0'''' output if the results of said summation are less than said threshold; and n+1 parallel-connected adder stages, the first one of said n+1 adder stages receiving the least two significant bits and weighting them by a factor of 20 and further receiving the output of said first adder-comparator stage and weighting it by a factor of -21, said first adder stage summing all of said weighted inputs, the second one of said n+1 adder stages receiving a carry input from said first adder-comparator stage and the two next bits of higher significance and weighting them by factors of 20, and further receiving the output of said second adder-comparator stage and weighting it by a factor of -21, said second adder stage summing all of said weighted inputs, the ith one of said n+1 adder stages receiving a carry input from the i-1th adder-comparator stage and the i+1th most significant two bits and weighting them by a factor of 20 and further receiving the output of said ith adder-comparator stage and weighting it by a factor of -21, said ith adder stage summing all of said weighted inputs, the n+1th one of said adder stages receiving the carry input from said nth adder-comparator stage and the n+1th two most significant bits and weighting them by a factor of 20, and further receiving the output of said n+1th adder-comparator stage and weighting it by a factor of -21, said n+1th adder stage summing all of said weighted inputs; and the output of said first adder stage providing the least significant output digit, the output of the ith adder stage providing the ith most significant output digit, the output of the n+1th adder stage providing the n+1th most significant output digit and the output of said n+1th adder-comparator stage provides a carry output.

Claim 11

A high speed parallel digital adder circuit for adding two digital numbers each comprising n+1 bits, which comprises: n+1 logic circuits, each logic circuit including an adder-comparator stage and an adder stage, including an operational amplifier, the first one of said n+1 adder-comparator stages receiving the two bits of least significance and weighting them by a factor of 20, said first adder-comparator stage further summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the first one of said n+1 adder stages receiving the same two bits of least significance and weighting them by a factor of 20 and further receiving the output of said first adder-comparator stage and weighting it by a factor of -21 and then summing all of said weighted inputs, the ithe one of said n+1 adder comparator stages receiving the ith two bits of next significance and further receiving the output of the i-1th adder-comparator stage, all of said inputs being weighted by a factor of 20, said ith adder-comparator stage summing all of said weighted inPuts to provide a ''''1'''' output if the results of said summation exceed a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the ith one of said adder stages receiving the same two ith bits of next significance and the output of the i-1th adder-comparator stage and weighting them by a factor of 20 and further receiving the output of the ith adder-comparator stage and weighting it by a factor of -21, and then summing all of said weighted outputs, the n+1th one of said adder-comparator stages receiving the two most significant bits and the output of the nth adder-comparator stage all of said inputs being weighted by a factor of 20, said n+1th adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation are equal to or greater than a threshold set equal to 21 and to produce a ''''0'''' output if said results are smaller than said threshold, the n+1th one of said adder stages receiving the same two most significant bits and weighting them by a factor of 20 and further receiving the output of the n+1th adder-comparator stage and weighting it by a factor of -21, and then summing all of said weighted inputs, the output of the first through the n+1th adder stages providing the least significant output to the n+1th significant output, respectively, and the output of the n+1th adder-comparator stage provides carry output.

Claim 12

A high speed parallel digital adder circuit for adding two digital numbers each comprising n+1 bits, which comprises: n+1 logic circuits, each logic circuit including an adder-comparator stage and an adder stage, including an operational amplifier, the first one of said n+1 adder-comparator stages receiving the two bits of least significance and weighting them by a factor of 20, said first adder-comparator stage further summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the first one of said n+1 adder stages receiving the same two bits of least significance and weighting them by a factor of 20 and further receiving the output of said first adder-comparator stage and weighting it by a factor of -21 and then summing all of said weighted inputs, the ithe one of said n+1 adder comparator stages receiving the ith two bits of next significance and further receiving the output of the i-1th adder-comparator stage, all of said inputs being weighted by a factor of 20, said ith adder-comparator stage summing all of said weighted inPuts to provide a ''''1'''' output if the results of said summation exceed a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the ith one of said adder stages receiving the same two ith bits of next significance and the output of the i-1th adder-comparator stage and weighting them by a factor of 20 and further receiving the output of the ith adder-comparator stage and weighting it by a factor of -21, and then summing all of said weighted outputs, the n+1th one of said adder-comparator stages receiving the two most significant bits and the output of the nth adder-comparator stage all of said inputs being weighted by a factor of 20, said n+1th adder-comparator stage summing all of said weighted inputs to produce a ''''1'''' output if the results of said summation are equal to or greater than a threshold set equal to 21 and to produce a ''''0'''' output if said results are smaller than said threshold, the n+1th one of said adder stages receiving the same two most significant bits and weighting them by a factor of 20 and further receiving the output of the n+1th adder-comparator stage and weighting it by a factor of -21, and then summing all of said weighted inputs, the output of the first through the n+1th adder stages providing the least significant output to the n+1th significant output, respectively, and the output of the n+1th adder-comparator stage provides carry output.

Claim 13

A high-speed, parallel digital adder circuit for adding two digital numbers, each comprising (n+1) bits, which comprises: (n+1) logic circuits, each logic circuit including an adder-comparator stage, and an adder stage including an operational amplifier, said (n+1) logic circuits being grouped sequentially for every successive j circuits, the first adder-comparator stage of the first group of j circuits receiving the two bits of least significance and weighting them by a factor of 20, and, further, summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the first adder stage of said first group of j circuits receiving the same two bits of least significance and weighting them by a factor of 20 and further receiving the output of said first-adder comparator stage of the first group of j circuits and weighting it by a factor of -21 and then summing all of said weighted inputs; the second adder-comparator stage of the first group of j circuits receiving the two bits of least significance and the two bits of the next higher significance and weighting them by factors of 20 and 21, respectively, and further summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 22 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the second adder stage of the first group of j circuits receiving the two bits of the next higher significance and the output of said first adder-comparator stage of the first group of j circuits and weighting them by a factor of 20 and further receiving the output of said second adder-comparator stage of the first group of j circuits and weighting it by a factor of -21 and then summing all said weighted inputs; the jth adder-comparator stage of said first group of j circuits receiving the least two significAnt bits through the jth pair of bits and weighting them by factors of 20 through 2j 1, respectively, said jth adder-comparator stage of said first group of j circuits further summing all said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 2j and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the jth adder stage of said first group of j circuits receiving the jth pair of bits and the output of the (j-1)th adder-comparator stage of said first group of j circuits and weighting it by a factor of -2'' and then summing all of said weighted inputs; the 1st, 2nd ... jth adder-comparator stages of the successive (K-1) groups of j circuits similarly operating on the (j+1)th, (2j+1)th ... ((K-1)j+1)th; (j+1,2)th, (2j+1,2)th ... ((K-1)j+1, 2)th; and the (j+1, 2, 2)th, (2j+1, 2, 3)th l ... ((K-1)j+1, 2, 3)th pairs of bits, respectively, and the 1st, 2nd, ... jth adder stages of the successive (K-1) groups of j circuits similarly operating on the (j+1)th, (2j+1)th ... ((k-1)j+1)th; (j+2)th, (2j+2)th ... ((K-1)j+2)th; and the (j+3)th, (2j+3)th ... ((K-1)j+3)th pairs of bits, respectively; each adder-comparator stage in the second group of j circuits receiving as an input the output of the jth adder-comparator stage in said first group of j circuits and weighting it by a factor of 20; each adder-comparator stage in the Kth group of j circuits receiving as an output of the jth adder-comparator stage of the preceding (K-1)th group of j circuits and weighting it by a factor of 20; the largest number of inputs to the adder-comparator stages in each group being less than 2j 1, the outputs of the first adder stage in said first group of j circuits through the jth adder stage in said Kth group of j circuits providing the least significant output through the most significant output, respectively, and the output of the jth adder-comparator stage of said Kth group of j circuits providing a carry-output, whereby, said two digital numbers, each having a large number of digits, are added.

Claim 14

A high-speed, parallel digital adder circuit for adding two digital numbers, each comprising (n+1) bits, which comprises: (n+1) logic circuits, each logic circuit including an adder-comparator stage, and an adder stage including an operational amplifier, said (n+1) logic circuits being grouped sequentially for every successive j circuits, the first adder-comparator stage of the first group of j circuits receiving the two bits of least significance and weighting them by a factor of 20, and, further, summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 21 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the first adder stage of said first group of j circuits receiving the same two bits of least significance and weighting them by a factor of 20 and further receiving the output of said first-adder comparator stage of the first group of j circuits and weighting it by a factor of -21 and then summing all of said weighted inputs; the second adder-comparator stage of the first group of j circuits receiving the two bits of least significance and the two bits of the next higher significance and weighting them by factors of 20 and 21, respectively, and further summing said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 22 and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the second adder stage of the first group of j circuits receiving the two bits of the next higher significance and the output of said first adder-comparator stage of the first group of j circuits and weighting them by a factor of 20 and further receiving the output of said second adder-comparator stage of the first group of j circuits and weighting it by a factor of -21 and then summing all said weighted inputs; the jth adder-comparator stage of said first group of j circuits receiving the least two significAnt bits through the jth pair of bits and weighting them by factors of 20 through 2j 1, respectively, said jth adder-comparator stage of said first group of j circuits further summing all said weighted inputs to produce a ''''1'''' output if the results of said summation equals or exceeds a threshold set equal to 2j and to produce a ''''0'''' output if the results of said summation are smaller than said threshold, the jth adder stage of said first group of j circuits receiving the jth pair of bits and the output of the (j-1)th adder-comparator stage of said first group of j circuits and weighting it by a factor of -2'' and then summing all of said weighted inputs; the 1st, 2nd ... jth adder-comparator stages of the successive (K-1) groups of j circuits similarly operating on the (j+1)th, (2j+1)th ... ((K-1)j+1)th; (j+1,2)th, (2j+1,2)th ... ((K-1)j+1, 2)th; and the (j+1, 2, 2)th, (2j+1, 2, 3)th l ... ((K-1)j+1, 2, 3)th pairs of bits, respectively, and the 1st, 2nd, ... jth adder stages of the successive (K-1) groups of j circuits similarly operating on the (j+1)th, (2j+1)th ... ((k-1)j+1)th; (j+2)th, (2j+2)th ... ((K-1)j+2)th; and the (j+3)th, (2j+3)th ... ((K-1)j+3)th pairs of bits, respectively; each adder-comparator stage in the second group of j circuits receiving as an input the output of the jth adder-comparator stage in said first group of j circuits and weighting it by a factor of 20; each adder-comparator stage in the Kth group of j circuits receiving as an output of the jth adder-comparator stage of the preceding (K-1)th group of j circuits and weighting it by a factor of 20; the largest number of inputs to the adder-comparator stages in each group being less than 2j 1, the outputs of the first adder stage in said first group of j circuits through the jth adder stage in said Kth group of j circuits providing the least significant output through the most significant output, respectively, and the output of the jth adder-comparator stage of said Kth group of j circuits providing a carry-output, whereby, said two digital numbers, each having a large number of digits, are added.