Patent US3354367A successfully refreshed from Google Patents.
Patent US3585608A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3585608A Expired / Lapsed US ⏱️ 0.0 years remaining

Random access memory

Assignee: HP Inc
•
Filing: 1969-05-21
•
Granted: 1971-06-15
•
Expires: 1989-05-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Internal control and subroutine logic transfers data between a keyboard input, a random access memory, and a plurality of flipflop registers to perform arithmetic operations and transfers the results of these operations to a cathode-ray tube output display. Power switching is employed in the internal control and subroutine logic so that the subroutines and instructions of the calculator are supplied with power only when they are to be executed. When a random access memory cycle is required, it is automatically interposed between the otherwise regularly recurring logic cycles by the internal control and subroutine logic. Encoded transfer vectors are stored and decoded by the subroutine logic to permit unrestricted subroutine returns. In the keyboard input two power supply returns are employed to define one bit of the keyboard encoder. The random access memory is partitioned into one portion addressed by a single bit in an address register and into another, larger portion addressed by the remaining bits in the address register. Each flip-flop of the machine is a J-K flip-flop provided with an adjustable threshold for noise immunity and with a high internal gain on the J-K inputs. In the cathode-ray tube output display, a recurring pattern generated by integration in only two directions is selectively blanked to display the results of the operations performed by the calculator. A tester may be connected to the machine for allowing all subroutines to be operated in a single step mode. The tester is provided with switches for initializing any internal state of the machine or stopping normal execution under any prescribed conditions and with apparatus for accessing the random access memory.

Inventors

  • 👤 Thomas E Osborne

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 08:07
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/32; G06F11/324; G06F11/325; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318522; G01R31/318525; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3287; G06F11/22; G06F11/26; G06F11/273; G06F15/00; G06F15/02; G06F3/00; G06F3/01; G06F3/02; G06F3/0227; G06F3/048; G06F3/0487; G06F3/0489; G06F3/14; G06F3/153; G06F7/00; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486; G09; G09G; G09G1/00; G09G1/06; G09G1/14; G09G1/18; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03M; H03M11/00; H03M11/22; Y; Y02; Y02D; Y02D10/00

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 78 words
A random access memory having a group of memory channels, a group of flip-flops connected through a group of gates to the memory for denoting all of the channels in said group of memory channels except one, a single gate for denoting the One remaining channel in said group of memory channels, and an extra flip-flop connected to said group of gates and to said single gate for alternatively blocking the group of gates or the single gate.
Claim 2
Dependent Claim 78 words
A random access memory having a group of memory channels, a group of flip-flops connected through a group of gates to the memory for denoting all of the channels in said group of memory channels except one, a single gate for denoting the One remaining channel in said group of memory channels, and an extra flip-flop connected to said group of gates and to said single gate for alternatively blocking the group of gates or the single gate.
Claim 3
Dependent Claim 78 words
A memory system comprising: a memory having a plurality of memory addresses; first selection means connected to said memory for individually addressing at least one of a group of said memory addresses; second selection means connected to said memory for individually addressing all of the remaining memory addresses in said group of memory addresses; and control means connected to said first and second selection means for alternatively blocking either the first selection means or the second selection means.
Claim 4
Dependent Claim 78 words
A memory system comprising: a memory having a plurality of memory addresses; first selection means connected to said memory for individually addressing at least one of a group of said memory addresses; second selection means connected to said memory for individually addressing all of the remaining memory addresses in said group of memory addresses; and control means connected to said first and second selection means for alternatively blocking either the first selection means or the second selection means.
Claim 5
Dependent Claim 106 words
A memory system as in claim 2 wherein: said first selection means comprises at least one flip-flop connected by a first gating circuit to said memory for individually addressing at least one of said group of said memory addresses; said second selection means comprises a group of flip-flops connected by a second gating circuit to said memory for individually addressing all of the remaining memory addresses of said group in memory addresses; and said control means comprises said one flip-flop, said one flip-flop being connected to both said first and second gating circuits for alternatively blocking either the first gating circuit or the second gating circuit.
Claim 6
Dependent Claim 15 words
A memory system as in claim 3 wherein said memory comprises a random access memory.
Claim 7
Dependent Claim 116 words
A memory system comprising: a memory having a plurality of groups of memory addresses; first selection means connected to said memory for individually addressing each of said groups of memory addresses; second selection means connected to said memory for individually addressing at least one of the memory addresses in each of said groups of memory addresses addressed by said first selection means; third selection means connected to said memory for individually addressing all of the remaining memory addresses in each of said groups of memory addresses addressed by said first selection means; and control means connected to said second and third selection means for alternatively blocking either the second selection means or the third selection means.
Claim 8
Dependent Claim 116 words
A memory system comprising: a memory having a plurality of groups of memory addresses; first selection means connected to said memory for individually addressing each of said groups of memory addresses; second selection means connected to said memory for individually addressing at least one of the memory addresses in each of said groups of memory addresses addressed by said first selection means; third selection means connected to said memory for individually addressing all of the remaining memory addresses in each of said groups of memory addresses addressed by said first selection means; and control means connected to said second and third selection means for alternatively blocking either the second selection means or the third selection means.
Claim 9
Dependent Claim 157 words
A memory system as in claim 5 wherein: said first selection means comprises a first group of flip-flops connected by a first gating circuit to said memory for individually addressing each of said groups of memory addresses; said second selection means comprises at least one flip-flop connected by a second gating circuit to said memory for individually addressing at least one of the memory addresses in each of said groups of memory addresses addressed by said first group of flip-flops; said third selection means comprises a second group of flip-flops connected by a third gating circuit to said memory for individually addressing all of the remaining memory addresses in each of said groups of memory addresses addressed by said first group of flip-flops; and said control means comprises said one flip-flop, said one flip-flop being connected to both said second and third gating circuits for alternatively blocking either the second gating circuit or the third gating circuit.
Claim 10
Dependent Claim 15 words
A memory system as in claim 5 wherein said memory comprises a random access memory.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-06-14 1974-12-14 1975-06-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-06-14 1978-12-14 1979-06-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-06-14 1982-12-14 1983-06-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag