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US3585592A Expired / Lapsed US ⏱️ 0.0 years remaining

Character recognition system with character edge detection capability

Assignee: NEC Corp
•
Filing: 1969-02-18
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Granted: 1971-06-15
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Expires: 1989-02-18
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Abstract

Abstract A system for recognizing and reproducing a preselected numerical character formed in ink on a transparent background, including: optical conversion of background and ink portions of the character into ''''0'''' and ''''1'''' signals, respectively, which are stored in a pattern in a shift register; logic means utilizing the ''''0'''' and ''''1'''' shift register stored signals row-by-row to produce signals representing particular features of successively scanned segments of the ink; discriminating circuit means selectively energizing certain circuits thereof representing typical segments of a known character corresponding to the scanned character in response to the particular feature signals; and receiving means activated by the selectively energized discrimination circuit means at the end of the utilization of the stored ''''0'''' and ''''1'''' signals to reproduce the scanned character in terms of the ''''0'''' and ''''1'''' signal pattern stored in the shift register.

Inventors

  • 👤 Kazuo Kiji
  • 👤 Yukio Hoshino

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 07:52
CPC Classifications
G; G06; G06V; G06V30/00; G06V30/10; G06V30/18; G06V30/1801; G06V30/18076

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 346 words
A system for recognizing and reproducing a preselected character formed with a preselected color ink on a transparent background, comprising: optical means for converting discrete portions of said character background and ink into ''''0'''' and ''''1'''' signals, respectively, and for producing a synchronizing signal; a shift register comprising discrete areas arranged in rows and columns, each area common to one row and column, for storing said ''''0'''' 0''''1'''' 1in a pattern; logic means activated by said synchronizing signal to scan said areas in a bottom row of said regiSter simultaneously in lefthand-to-right-hand and right-hand-to-left-hand directions for sensing ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein to produce output ''''1'''' signals to represent left-hand and right-hand edges of successively scanned ink segments; said last-mentioned means shifting down said ''''0'''' and ''''1'''' signals in a next-to-the-bottom register row to replace said ''''0'''' and ''''1'''' signals then in said bottom rows while at the same time shifting down said ''''0'''' and ''''1'''' signals in all of the remaining register rows by one row at a time until all of said ''''0'''' and ''''1'''' signals remaining in said shift register are sensed in said shift register bottom row; logic means counting said ''''1'''' signals due to said ''''0 '''' to ''''1'''' transitions in said register bottom row as sensed only in successive left-hand-to-right-hand scanning directions; logic means activated by said left-hand and right-hand edge ''''1'''' signals and said counted ''''1'''' signals for producing successive signals representing particular features of successively scanned segments of said ink character; discriminating circuit means including a plurality of groups of discrete electric circuits, each circuit group representing one of a plurality of typical segments of said scanned character; said circuits of each of said circuit groups selectively energized one at a time in response to said feature means successive output signals; and receiving means activated by said energized circuits after all of said ''''0'''' and ''''1'''' signals stored in said shift register are sensed for reproducing said scanned character in terms of said ''''0'''' and ''''1'''' signal pattern stored in said last mentioned register.
Claim 2
Independent Claim 346 words
A system for recognizing and reproducing a preselected character formed with a preselected color ink on a transparent background, comprising: optical means for converting discrete portions of said character background and ink into ''''0'''' and ''''1'''' signals, respectively, and for producing a synchronizing signal; a shift register comprising discrete areas arranged in rows and columns, each area common to one row and column, for storing said ''''0'''' 0''''1'''' 1in a pattern; logic means activated by said synchronizing signal to scan said areas in a bottom row of said regiSter simultaneously in lefthand-to-right-hand and right-hand-to-left-hand directions for sensing ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein to produce output ''''1'''' signals to represent left-hand and right-hand edges of successively scanned ink segments; said last-mentioned means shifting down said ''''0'''' and ''''1'''' signals in a next-to-the-bottom register row to replace said ''''0'''' and ''''1'''' signals then in said bottom rows while at the same time shifting down said ''''0'''' and ''''1'''' signals in all of the remaining register rows by one row at a time until all of said ''''0'''' and ''''1'''' signals remaining in said shift register are sensed in said shift register bottom row; logic means counting said ''''1'''' signals due to said ''''0 '''' to ''''1'''' transitions in said register bottom row as sensed only in successive left-hand-to-right-hand scanning directions; logic means activated by said left-hand and right-hand edge ''''1'''' signals and said counted ''''1'''' signals for producing successive signals representing particular features of successively scanned segments of said ink character; discriminating circuit means including a plurality of groups of discrete electric circuits, each circuit group representing one of a plurality of typical segments of said scanned character; said circuits of each of said circuit groups selectively energized one at a time in response to said feature means successive output signals; and receiving means activated by said energized circuits after all of said ''''0'''' and ''''1'''' signals stored in said shift register are sensed for reproducing said scanned character in terms of said ''''0'''' and ''''1'''' signal pattern stored in said last mentioned register.
Claim 3
Dependent Claim 72 words
The system according to claim 1, in which said scanning logic means includes an AND gate inhibited in response to first sensings of said ''''0'''' to ''''1'''' transitions as said shift register bottom row is scanned in left-hand-to-right-hand directions to represent said respective ink segment left-hand edges for preventing second sensings of said ''''0'''' to ''''1'''' transitions at said last-mentioned ink segment edges as ink segments are scanned in said last-mentioned directions.
Claim 4
Dependent Claim 73 words
The system according to claim 1, in which said scanning logic means includes an AND gate inhibited in response to first sensings of said ''''1'''' to ''''0'''' transitions as said shift register bottom row is scanned in left-hand-to-right-hand directions to represent said respective ink segment right-hand edges for preventing second sensings of said ''''1'''' to ''''0'''' transitions at said last-mentioned ink segment edges as said ink segments are scanned in said last-mentioned directions.
Claim 5
Dependent Claim 71 words
The system according to claim 1, in which said scanning logic means includes an AND gate inhibited in response to first sensings of said ''''0'''' to ''''1'''' transitions as said shift register bottom row is scanned in right-hand-to-left-hand directions to represent said respective ink segment right-hand edges for preventing second sensings of said ''''0'''' to ''''1'''' transitions at said last-mentioned edges as said ink segments are scanned in said last-mentioned directions.
Claim 6
Dependent Claim 73 words
The system according to claim 1 in which said scanning logic means includes an AND gate inhibited in response to first sensings of said ''''1'''' to ''''0'''' transitions as said shift register bottom row is scanned in right-hand-to-left-hand directions to represent said respective ink segment left-hand edges for preventing second sensings of said ''''1'''' to ''''0'''' transitions at said last-mentioned ink segment edges as said ink segments are scanned in said last-mentioned directions.
Claim 7
Dependent Claim 175 words
The system according to claim 1 in which said scanning logic means includes pulse generating means activated by said optical means synchronizing signal to generate trains of equally spaced timing pulses of which each train comprises certain pulses, equal in number to the number of said areas in each of said shift register rows, to scan said areas one at a time in said shift register bottom row simultaneously in said left-hand-to-right-hand and right-hand-to-left-hand directions for sensing said ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein to produce said ''''1'''' signals; each of said pulse trains also comprising a last pulse actuating said shift register to shift down said ''''0'''' and ''''1'''' signals in said next-to-the-bottom row to replace said ''''0'''' and ''''1'''' signals then in said bottom row while at the same time shifting down said ''''0'''' and ''''1'''' signals in all of the remaining register rows one row at a time until all of said ''''0'''' and ''''1'''' signals remaining in said shift register are sensed in said shift register bottom row.
Claim 8
Dependent Claim 56 words
The system according to claim 2 in which said scanning logic means includes two OR gates for producing successive pairs of time-serial output binary signals in response to said simultaneous left-hand-to-right-hand and right-hand-to-left-hand directional scanning of said areas in said shift register bottom row for sensing said ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein.
Claim 9
Dependent Claim 36 words
The system according to claim 7 which includes additional logic means activated by said OR gate output binary signals for producing said ''''1'''' signals to represent said left-hand and right-hand edges of said successively scanned segments.
Claim 10
Dependent Claim 125 words
The system according to claim 8 in which said counting means comprises: a 2-bit counter for counting the number of said ''''0'''' to ''''1'''' transitions occurring in said shift register bottom row as representing said ''''0'''' and ''''1'''' transitions in said respective shift register rows as said shift register bottom row is scanned in said left-hand-to-right-hand direction; said last-mentioned counter activated to count 1 and 2 in response to one and two occurrences of said ''''0'''' to ''''1'''' transitions, respectively, in said last-mentioned bottom row; and further logic means activated by one of said one and two count in said last-mentioned counter to produce further output ''''1'''' signals, each representing the number of ''''0'''' to ''''1'''' transitions in successively scanned ink segments of said character.
Claim 11
Dependent Claim 47 words
The system according to claim 9 in which said feature producing logic means is activated by said additional logic means output ''''1'''' signals and said further logic means further output ''''1'''' signals for producing said successive signals representing said particular features of said successively scanned ink segments.
Claim 12
Dependent Claim 74 words
The system according to claim 10 which includes supplementary means for counting said last timing pulses in successive scanning pulse trains to such number as required to scan said shift register bottom row until all of said ''''0'''' and ''''1'''' signals stored in said respective shift register rows are sensed to produce a recognition command pulse, whereby said discriminating means is stimulated to read out said energized circuits thereof to activate said receiving means.
Claim 13
Independent Claim 527 words
A system for recognizing and reproducing a numerical character formed with a preselected color ink on a transparent background, comprising: optical means for converting discrete portions of said character background and ink into ''''0'''' and ''''1'''' signals, respectively, and for producing a synchronizing signal; a shift register comprising discrete areas arranged in rows and columns, each area common to one row and column, for storing said ''''0'''' and ''''1'''' signals in a pattern; pulse generating means activated by said synchronizing signal for generating trains of scanning pulses of which each train includes certain pulses, equal in number to the number of said areas in each of said register rows, and a last pulse; logic means activated by said certain pulses of successive scanning pulse trains to scan said areas one at a time in a bottom row of said register simultaneously in left-hand-to-right-hand and right-hand-to-left-hand directions for sensing ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein to produce successive simultaneous pairs of time-serial binary output signals while thereafter said last pulses in said successive scanning pulse trains shift down said ''''0'''' and ''''1'''' signals in a next-to-the-bottom row to replace said ''''0'''' and ''''1'''' signals in said bottom row and at the same time shift down said ''''0'''' and ''''1'''' signals in the remaining rows of said register by one row at a time until said ''''0'''' and ''''1'''' signals in all of said register rows are sensed in said register bottom row; OR gate logic means activated by discrete scanning pulses in said successive trains thereof for producing corresponding output signals; logic edge tracer means activated by said scanning means binary output signals, said generating means pulse train last pulses and said OR gate means output signals for producing output signals to represent left-hand and right-hand edges of successively scanned ink segments of said character; logic means counting ''''0'''' to ''''1'''' transitions in said register bottom row as sensed only in successive left-hand-to-right-hand directions for producing output signals representing the number of said latter transitions occurring in adjacent rows of said register as sensed in turn in said register bottom row; logic means activated by said edge tracer means output signals and said counting means output signals for producing successive signals to represent particular features of successively scanned ink segments of said character; discriminating circuit means including a plurality of groups of electric circuits, each circuit group representing one of a plurality of typical segments of said scanned ink character; said circuits of each of said circuit groups selectively energized one at a time in response to said feature means successive output signals; supplementary counting means for counting said last pulses in successive scanning pulse trains to such number as required to scan said register bottom row until all of said ''''0'''' and ''''1'''' signals stored in said register pattern are sensed to produce a recognition command signal, whereby said discriminating circuit means is activated to read out said energized circuits therein; and receiving means activated by said discriminating means energized circuits as read out therefrom for reproducing said scanned ink character in terms of said ''''0'''' and ''''1'''' signal pattern stored in said register.
Claim 14
Independent Claim 527 words
A system for recognizing and reproducing a numerical character formed with a preselected color ink on a transparent background, comprising: optical means for converting discrete portions of said character background and ink into ''''0'''' and ''''1'''' signals, respectively, and for producing a synchronizing signal; a shift register comprising discrete areas arranged in rows and columns, each area common to one row and column, for storing said ''''0'''' and ''''1'''' signals in a pattern; pulse generating means activated by said synchronizing signal for generating trains of scanning pulses of which each train includes certain pulses, equal in number to the number of said areas in each of said register rows, and a last pulse; logic means activated by said certain pulses of successive scanning pulse trains to scan said areas one at a time in a bottom row of said register simultaneously in left-hand-to-right-hand and right-hand-to-left-hand directions for sensing ''''0'''' to ''''1'''' and ''''1'''' to ''''0'''' transitions therein to produce successive simultaneous pairs of time-serial binary output signals while thereafter said last pulses in said successive scanning pulse trains shift down said ''''0'''' and ''''1'''' signals in a next-to-the-bottom row to replace said ''''0'''' and ''''1'''' signals in said bottom row and at the same time shift down said ''''0'''' and ''''1'''' signals in the remaining rows of said register by one row at a time until said ''''0'''' and ''''1'''' signals in all of said register rows are sensed in said register bottom row; OR gate logic means activated by discrete scanning pulses in said successive trains thereof for producing corresponding output signals; logic edge tracer means activated by said scanning means binary output signals, said generating means pulse train last pulses and said OR gate means output signals for producing output signals to represent left-hand and right-hand edges of successively scanned ink segments of said character; logic means counting ''''0'''' to ''''1'''' transitions in said register bottom row as sensed only in successive left-hand-to-right-hand directions for producing output signals representing the number of said latter transitions occurring in adjacent rows of said register as sensed in turn in said register bottom row; logic means activated by said edge tracer means output signals and said counting means output signals for producing successive signals to represent particular features of successively scanned ink segments of said character; discriminating circuit means including a plurality of groups of electric circuits, each circuit group representing one of a plurality of typical segments of said scanned ink character; said circuits of each of said circuit groups selectively energized one at a time in response to said feature means successive output signals; supplementary counting means for counting said last pulses in successive scanning pulse trains to such number as required to scan said register bottom row until all of said ''''0'''' and ''''1'''' signals stored in said register pattern are sensed to produce a recognition command signal, whereby said discriminating circuit means is activated to read out said energized circuits therein; and receiving means activated by said discriminating means energized circuits as read out therefrom for reproducing said scanned ink character in terms of said ''''0'''' and ''''1'''' signal pattern stored in said register.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-06-14 1974-12-14 1975-06-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-06-14 1978-12-14 1979-06-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-06-14 1982-12-14 1983-06-15 $7700.00 Window Closed / Lapsed

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