Patent US3585591A successfully refreshed from Google Patents.
US3585591A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for determining the correct position of a character in a character reader
Assignee: Telefunken Patentverwertungs GmbH
•
Filing: 1968-08-14
•
Granted: 1971-06-15
•
Expires: 1988-08-14
Abstract
Abstract An arrangement for determining the instant when a character traversing the scanning field of a character reader is in the proper position to be read including a plurality of memory elements for storing information in binary form relating to the dark and light pattern appearing in the scanning field and signal processing means connected to the memory elements for producing weighted outputs in each half of the scanning field at spaced intervals and arranged to produce a reading signal when the weighted outputs relating to the two halves of the scanning field differ from one another by less than a predetermined amount.
Inventors
- 👤 Paul Hauff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:59
CPC Classifications
G; G06; G06V; G06V30/00; G06V30/10; G06V30/14; G06V30/146
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
315 words
A circuit arrangement for determining the correct reading position of a character represented by a serial sequence of binary bits in a shift register which is composed of a plurality of sections divided into two substantially equal portions and which receives the whole pattern content of a scanning field containing the character and scanned by sensing means in consecutive scanning sections corresponding to the shift register sections, said arrangement comprising, in combination: a. a plurality of output gates each connected to a respective shift register section for receiving the binary bits associated with each consecutive scanning section; b. adder means connected to said gates for summing the number of occurrences of one binary bit value in each section of the shift register, said adder means being divided into two groups each associated with a respective shift register portion; c. temporary storage means connected to the outputs of said adder means for temporarily storing the adder means outputs and divided into two groups each associated with a respective shift register portion; d. each group of said adder means forming a respective unit with a respective group of said storage means; e. summing means connected to said adder means and storage means for causing each unit thereof to periodically produce a weighted output Sigma Alpha i.Zi, where Zi represents the number of occurrences of the one binary bit value in a section of the shift register and Alpha i is a weighting value corresponding to the position of that section in the shift register, at successive instants corresponding to successive positions of the character being investigated relative to the scanning field; and f. position indicating and difference determining means connected to said summing means for producing an indication of the difference between the simultaneously appearing weighted outputs from said two units and for producing a correct position signal when such difference is less than a predetermined value.
Claim 2
Dependent Claim
315 words
A circuit arrangement for determining the correct reading position of a character represented by a serial sequence of binary bits in a shift register which is composed of a plurality of sections divided into two substantially equal portions and which receives the whole pattern content of a scanning field containing the character and scanned by sensing means in consecutive scanning sections corresponding to the shift register sections, said arrangement comprising, in combination: a. a plurality of output gates each connected to a respective shift register section for receiving the binary bits associated with each consecutive scanning section; b. adder means connected to said gates for summing the number of occurrences of one binary bit value in each section of the shift register, said adder means being divided into two groups each associated with a respective shift register portion; c. temporary storage means connected to the outputs of said adder means for temporarily storing the adder means outputs and divided into two groups each associated with a respective shift register portion; d. each group of said adder means forming a respective unit with a respective group of said storage means; e. summing means connected to said adder means and storage means for causing each unit thereof to periodically produce a weighted output Sigma Alpha i.Zi, where Zi represents the number of occurrences of the one binary bit value in a section of the shift register and Alpha i is a weighting value corresponding to the position of that section in the shift register, at successive instants corresponding to successive positions of the character being investigated relative to the scanning field; and f. position indicating and difference determining means connected to said summing means for producing an indication of the difference between the simultaneously appearing weighted outputs from said two units and for producing a correct position signal when such difference is less than a predetermined value.
Claim 3
Dependent Claim
105 words
An arrangement as defined in claim 1 wherein said adder means are constituted by a plurality of full adders, each connected to a respective section of the shift register, and said temporary storage means are constituted by a plurality of bistable intermediate memory elements each associated with a respective full adder and each having an input connected to one output of its associated full adder, wherein the output of each said intermediate memory element is connected to the operand input of its associated full adder and the carry output of each full adder is connected to the carry input of the next succeeding full adder.
Claim 4
Dependent Claim
50 words
An arrangement as defined in claim 2 wherein said temporary storage means further comprise an additional set of intermediate memory elements for each said unit, with the memory elements of each said set having an input connected to the carry output of the last full adder of its associated unit.
Claim 5
Dependent Claim
137 words
An arrangement as defined in claim 3 wherein one said unit further comprises a plurality of further full adders equal in number to the number of intermediate memory elements of said additional set of the other said unit, and said summing means include a plurality of gate elements each connected between the negated output of a respective intermediate memory element of said other unit and an input of a respective full adder or further full adder of said one unit, each said further full adder of said one unit having another input connected to the output of a respective intermediAte memory element of said additional set of said one unit, said arrangement further comprising means for enabling each of said gate elements each time the difference between said weighted outputs of said units is to be determined.
Claim 6
Dependent Claim
43 words
An arrangement as defined in claim 4 wherein said position indicating means are connected to the carry output of the last one of said further full adders for producing an indication when a change occurs in the signal appearing at said carry output.
Claim 7
Dependent Claim
34 words
An arrangement as defined in claim 1 wherein said adder means are connected to less than all of said sections of the shift registers, no connection being made to the last of said sections.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |