Abstract A semiconductor device and a method for fabricating the same which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a <100> plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the <100> oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a <100> plane with a plurality of semiconductor devices within the substrate is described. The devices are isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less than approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.
A monolithic integrated circuit structure comprising: a substrate of monocrystalline silicon material having a surface crystallographic orientation substantially parallel to the <100> plane; a substantially defect-free epitaxial semiconductor layer grown from said substrate wherein said layer has a surface crystallographic orientation substantially parallel to the <100> plane; a plurality of semiconductor devices located at least partially in said epitaxial layer; the said devices being so connected to produce desired circuits; the circuit area density being greater than about one circuit per 200 square mils; certain of said devices including a first diffused region partly in said substrate and partly in said epitaxial layer, a second diffused region of opposite conductivity from the first region in the surface of said epitaxial layer opposite to said substrate, a third diffused region of the said conductivity as the first in said second region, a fourth diffused region surrounding said second and third regions, and extending through the said epitaxial layer to the said substrate, and a layer of silicon dioxide over the surface of said epitaxial layer wherein said second, third and fourth diffused regions are formed; the density of interface states at the silicon dioxide to silicon interface between said body and said layer is less than approximately 2 X 1013 per cm.2; and the growth of said epitaxial layer is substantially perpendicular to the surface of said substrate, and the tolerance between said first region and said fourth region of said certain devices being less than approximately 0.3 mils.
Claim 2
Dependent Claim
30 words
The monolithic integrated circuit structure of claim 2 wherein the said structure is high current and high power, and having a current carrying capacity of more than about 1 amp.
Claim 3
Dependent Claim
30 words
The monolithic integrated structure of claim 2 wherein the said structure contains gold as an impurity to limit minority carrier lifetime and to improve the gain of the said circuits.
Claim 4
Dependent Claim
36 words
The monolithic integrated circuit structure of claim 2 wherein the said PN junction has a N region having a phosphorus concentration sufficient for satisfactory electrical contact and said junction is substantially free of phosphorus precipitation sites.
Claim 5
Dependent Claim
28 words
The monolithic integrated circuit of claim 2 wherein the said certain of the devices can be operated with significant gain at normalized currents as low as 0.0001 unit.