Patent US5623929A successfully refreshed from Google Patents.
Patent US3606573A successfully refreshed from Google Patents.
Patent US3585408A successfully refreshed from Google Patents.
US3585408A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mosfet circuit for extending the time duration of a clock pulse
Assignee: Shell USA Inc
•
Filing: 1969-07-17
•
Granted: 1971-06-15
•
Expires: 1989-07-17
Abstract
Abstract A MOSFET circuit is disclosed which is capable of generating a pulse of extended duration from a given clock pulse. The circuit includes regenerative mans effective at the end of the pulse of extended duration in order to provide a sharp termination thereof. A method of and means for controlling the amount by which the pulse duration is extended by controlling a voltage applied to the circuit are described.
Inventors
- 👤 Alton O Christensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:39
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; H03K3/00; H03K3/02; H03K3/353
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
307 words
A MOSFET circuit for generating, from an electrical pulse of given time duration, a further electrical pulse of increased time duration comprising: a. clock input means for said pulse of given time duration, output means for said pulse of increased time duration, and voltage input means; b. a first pair of MOSFETs having their sources connected together and to said clock input means and their drains connected together and to said output means, the gate of one of said first pair of MOSFETs being connected to said clock input means; c. a third MOSFET having its source connected to the gate of the other of said first pair of MOSFETs and its drain connected to said voltage input means, the gate of said third MOSFET being connected to said voltage input means through a resistive means; d. a fourth MOSFET having its source connected to ground and its drain connected to the gate of said other of said first pair of MOSFETs; e. a second pair of MOSFETs connected in series with the source of one of said second pair of MOSFETs connected to ground and the drain of the other of said second pair of MOSFETs connected to said voltage input, the common connection of said second pair of MOSFETs being connected to the gate of said fourth MOSFET, said one of said second pair of MOSFETs having its gate connected to said output line and said other of said second pair of MOSFETs having its gate connected to said voltage input means through a resistive means; and f. a seventh MOSFET having its source connected to ground and its drain connected to said gate of said third MOSFET and to said gate of said other one of said second pair of MOSFETs, the gate of saiD seventh MOSFET being connected to said clock input means.
Claim 2
Dependent Claim
307 words
A MOSFET circuit for generating, from an electrical pulse of given time duration, a further electrical pulse of increased time duration comprising: a. clock input means for said pulse of given time duration, output means for said pulse of increased time duration, and voltage input means; b. a first pair of MOSFETs having their sources connected together and to said clock input means and their drains connected together and to said output means, the gate of one of said first pair of MOSFETs being connected to said clock input means; c. a third MOSFET having its source connected to the gate of the other of said first pair of MOSFETs and its drain connected to said voltage input means, the gate of said third MOSFET being connected to said voltage input means through a resistive means; d. a fourth MOSFET having its source connected to ground and its drain connected to the gate of said other of said first pair of MOSFETs; e. a second pair of MOSFETs connected in series with the source of one of said second pair of MOSFETs connected to ground and the drain of the other of said second pair of MOSFETs connected to said voltage input, the common connection of said second pair of MOSFETs being connected to the gate of said fourth MOSFET, said one of said second pair of MOSFETs having its gate connected to said output line and said other of said second pair of MOSFETs having its gate connected to said voltage input means through a resistive means; and f. a seventh MOSFET having its source connected to ground and its drain connected to said gate of said third MOSFET and to said gate of said other one of said second pair of MOSFETs, the gate of saiD seventh MOSFET being connected to said clock input means.
Claim 3
Dependent Claim
40 words
A circuit as claimed in claim 1 wherein said gate of said third MOSFET and said gate of said other one of said second pair of MOSFETs are connected together and to said voltage input through a common resistive means.
Claim 4
Dependent Claim
38 words
A circuit as claimed in claim 1 wherein said resistive means through which said gate of said third MOSFET is connected to said voltage input means includes a MOSFET having its gate connected to said voltage input means.
Claim 5
Dependent Claim
44 words
A circuit as claimed in claim 1 wherein said resistive means through which said gate of said other one of said second pair of MOSFETs is connected to said voltage input means includes a MOSFET having its gate connected to said voltage input means.
Claim 6
Dependent Claim
29 words
A circuit as claimed in claim 2 wherein the said common resistance means is adopted to change in value inversely with a change in voltage at said voltage input.
Claim 7
Dependent Claim
24 words
A circuit as claimed in claim 5 wherein said common resistive means is a MOSFET having its gate connected to said voltage input means.
Claim 8
Dependent Claim
207 words
A circuit for generating, from an electrical pulse of given time duration, a further electrical pulse of increased time duration, said circuit comprising: a. input means for said pulse of given time duration and output means for said pulse of increased time duration; b. a first MOSFET and a second MOSFET having their sources connected together and to said input means and their drains connected together and to said output means, the gate of said first MOSFET being connected to said input means; c. charging means connected to the gate of said second MOSFET; d. discharging means connected to said gate of said second MOSFET; e. regenerative feedback means interconnecting said charging and said discharging means to enable said charging means to overpower said discharging means; f. deactivation means connected to said input means for causing said charging means and said regenerative feedback means to be deactivated by said electrical pulse of given time duration; g. activation means connected to said output means for causing said discharging means to be activated by said pulse of increased time duration; and h. time constant means for reactivating said charging means and said regenerative feedback means at a point in time after said electrical pulse of given duration has ended.
Claim 9
Dependent Claim
207 words
A circuit for generating, from an electrical pulse of given time duration, a further electrical pulse of increased time duration, said circuit comprising: a. input means for said pulse of given time duration and output means for said pulse of increased time duration; b. a first MOSFET and a second MOSFET having their sources connected together and to said input means and their drains connected together and to said output means, the gate of said first MOSFET being connected to said input means; c. charging means connected to the gate of said second MOSFET; d. discharging means connected to said gate of said second MOSFET; e. regenerative feedback means interconnecting said charging and said discharging means to enable said charging means to overpower said discharging means; f. deactivation means connected to said input means for causing said charging means and said regenerative feedback means to be deactivated by said electrical pulse of given time duration; g. activation means connected to said output means for causing said discharging means to be activated by said pulse of increased time duration; and h. time constant means for reactivating said charging means and said regenerative feedback means at a point in time after said electrical pulse of given duration has ended.
Claim 10
Dependent Claim
42 words
A circuit as claimed in claim 7 wherein said charging means comprises a voltage source connected to said gate of said second MOSFET through a third MOSFET the gate of which is connected to said voltage source through said time constant means.
Claim 11
Dependent Claim
41 words
A circuit as claimed in claim 7 wherein said discharging means comprises a further MOSFET connected between said gate of said second MOSFET and ground, the gate of said further MOSFET being connected to a voltage source through said activation means.
Claim 12
Dependent Claim
37 words
A circuit as claimed in claim 9 wherein said activation means comprises a still further MOSFET connected between said gate of said further MOSFET and said voltage source and having its gate connected to said output means.
Claim 13
Dependent Claim
40 words
A circuit as claimed in claim 10 wherein said regenerative feedback means comprises another MOSFET connected between said gate of said still further MOSFET and ground and having its gate connected to said voltage source through said time constant means.
Claim 14
Dependent Claim
43 words
A circuit as claimed in claim 7 wherein said deactivation means comprises yet another MOSFET connected between said charging means and ground and between said regenerative feedback means and ground, the gate of said yet another MOSFET being connected to said input means.
Claim 15
Dependent Claim
39 words
A circuit as claimed in claim 7 wherein said time constant means comprises a voltage source connected to said charging means and to said regenerative feedback means through a further MOSFET having its gate connected to said voltage source.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |