Fail-safe decoder circuits

Claim 2

A fail-safe decoder circuit constructed of individual logic elements which fail to a predicted state, said decoder comprising an input section having N binary input lines, where N>1, and N pairs of output lines, a logical decoding section having 2N input lines connected to the N pairs of output lines from said input section and having 2N output lines such that only one output line will be selected at any given time assuming correct operation of the decoder and an error detecting monitor connected to said plural output lines, said monitor being a logic block which fails to a predicted state said predicted state comprising an error indication for said decoder wherein no output line has been selected by said decoder.

Claim 3

A fail-safe decoder as set forth in claim 1 wherein said monitor comprises a logical NOR circuit.

Claim 4

A fail-safe decoder as set forth in claim 2 wherein said monitor NOR circuit produces a binary ''''0'''' output with any binary ''''1'''' input and a binary ''''1'''' output with all binary ''''0'''' inputs, or in the event of an internal failure which would affect the output condition.

Claim 5

A fail-safe decoder circuit as set forth in claim 1 wherein each of said N binary input lines of said input section is capable of being in a binary ''''1'''' or binary ''''0'''' state, said inPut section further including N single input logical NOR blocks connected to each input line which function as an inverter, the outputs of said N input lines and said N input NOR blocks providing N complementary input signal pairs to the decoder logic section, said decoder logic section including 2N decoder NOR logic blocks, each block providing a possible one of 2N output signals on said 2N decoder output lines wherein one output line emanates from each decoder NOR block, said input NOR logic blocks being designed to fail to a first binary state, said decoder NOR blocks being designed to fail to a second binary state and a monitor NOR block being designed to fail to said first binary logic state.

Claim 6

A fail-safe decoder as set forth in claim 4 wherein said decoder logic circuitry is composed entirely of said 2N logic blocks and wherein each NOR block has N individual inputs and wherein there is one and only one input to each block from each input or its associated inverter.

Claim 7

A fail-safe decoder circuit constructed exclusively of NOR logic elements wherein there are N binary decoder input lines each capable of being in a binary ''''1'''' or binary ''''0'''' state, and where N>1, a first logic level comprising N single input logical NOR blocks connected to each input line which function as inverters, the outputs of said N input lines and said N first level input NOR blocks providing N complementary input signal pairs to a second level of decoder logic, said second decoder logic level including 2N NOR logic blocks, each block providing a possible one of 2N output signals on 2N decoder output lines wherein one output line emanates from each decoder NOR logic block and wherein one and only one output line will be active at any one time when the decoder is operating properly, each said second level NOR blocks having N individual input lines and wherein there is one and only one input to each second level NOR block from each of said N complementary input signal pairs emanating from the N input lines and N first level input NOR blocks, said input connection for each second level NOR block effecting the binary decoding function, an error detecting monitor connected to said 2N output lines, said monitor being a NOR logic block, said monitor producing a first output state when either the monitor is defective or when the logical decoder circuitry fails to select an output line, said decoder NOR logic blocks being designed to fail to a second logical state wherein it will fail to select an output line if the logical block itself is defective, said input NOR block being designed to fail to said first logical state in the event of a failure within itself.

Claim 8

A fail-safe decoder circuit constructed exclusively of NOR logic elements wherein there are N binary decoder input lines each capable of being in a binary ''''1'''' or binary ''''0'''' state, and where N>1, a first logic level comprising N single input logical NOR blocks connected to each input line which function as inverters, the outputs of said N input lines and said N first level input NOR blocks providing N complementary input signal pairs to a second level of decoder logic, said second decoder logic level including 2N NOR logic blocks, each block providing a possible one of 2N output signals on 2N decoder output lines wherein one output line emanates from each decoder NOR logic block and wherein one and only one output line will be active at any one time when the decoder is operating properly, each said second level NOR blocks having N individual input lines and wherein there is one and only one input to each second level NOR block from each of said N complementary input signal pairs emanating from the N input lines and N first level input NOR blocks, said input connection for each second level NOR block effecting the binary decoding function, an error detecting monitor connected to said 2N output lines, said monitor being a NOR logic block, said monitor producing a first output state when either the monitor is defective or when the logical decoder circuitry fails to select an output line, said decoder NOR logic blocks being designed to fail to a second logical state wherein it will fail to select an output line if the logical block itself is defective, said input NOR block being designed to fail to said first logical state in the event of a failure within itself.

Claim 9

A fail-safe decoder circuit as set forth in claim 6, wherein said monitor NOR block is designed to fail to a binary ''''1'''' in the event of no output line selection by the decoder circuit per se or in the event of an internal failure, said decoder NOR logic blocks being designed to fail to a ''''0'''' binary state in the event of an internal failure which would erroneously affect the output, and said input NOR blocks being designed to fail to a logical ''''1'''' in the event of an internal failure which would erroneously affect the output.