Patent US3584266A successfully refreshed from Google Patents.
US3584266A
Expired / Lapsed
US
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Depletion layer capacitor in particular for monolithic integrated circuits
Assignee: TDK Micronas GmbH
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Filing: 1969-05-20
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Granted: 1971-06-08
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Expires: 1989-05-20
Abstract
Abstract This is a depletion layer capacitor which can be simultaneously formed with other planar transistors on a monolithic integrated circuit. The depletion layer capacitor achieves a high voltage breakdown by producing a PN junction which joins two highly doped regions of opposite conductivity type wherein said junction is established within an epitaxial layer of lower impurity concentration and doesn''t extend to the surface of said epitaxial layer.
Inventors
- 👤 Harald Schilling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:20
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/64; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10P; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/037; Y10S148/085; Y10S148/136; Y10S148/145
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
83 words
A depletion layer capacitor according to claim 1 wherein said capacitor is formed within a monolithic integrated circuit, further comprising: a ring region of the same conductivity type and approximately the same impurity concentration as said second region surrounding said depletion layer capacitor, said ring region extending from said one conductivity type material of said wafer to the surface of said layer for forming an electrical isolation barrier between said depletion layer capacitor and any other electrical components of the monolithic integrated circuit.
Claim 2
Dependent Claim
48 words
A depletion layer capacitor according to claim 1 wherein a third region of said opposite conductivity type is formed between said layer and said one conductivity material of said wafer, said third region having a higher impurity concentration than said layer, said third region surrounding said second region.
Claim 3
Dependent Claim
72 words
A depletion layer capacitor according to claim 1 wherein said second region is comprised of a stem extending from said one conductivity type material of said wafer to and within said first region, said means comprises a platform having the same conductivity type as said second region and being of lower impurity concentration than said second region, said platform extending further than said stem, and said platform being adjacent said first region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-07 | 1974-12-07 | 1975-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-07 | 1978-12-07 | 1979-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-07 | 1982-12-07 | 1983-06-08 | $7700.00 | Window Closed / Lapsed |