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US3584262A Expired / Lapsed US ⏱️ 0.0 years remaining

Solid-state on delay time delay apparatus

Assignee: Westinghouse Electric Corp
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Filing: 1968-05-28
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Granted: 1971-06-08
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Expires: 1988-05-28
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Abstract

Abstract A time delay trigger circuit which does not require a well regulated direct current supply voltage for accurate and reliable timing and does not cause heavy loading on the direct current supply prior to timing out still supplies ample trigger current to a controlled rectifier by diverting current which normally flows through a direct current regulator diode into the gate of the controlled rectifier. The controlled rectifier is maintained in a conducting state by using two ''''latching'''' resistors to provide a pulsating direct current load with a 90 electrical degree phase difference with the relay coil current, so that current through the controlled rectifier never decreases below its holding current until the line voltage is interrupted. After the circuit times out and the direct current supply diminishes, positive pulses are applied to the negative end of the timing capacitor, discharging the capacitor to zero voltage level so that the circuit will have an extremely short reset time after the timing cycle is completed.

Inventors

  • 👤 Wardell Gary

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 08:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; H03K17/292

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 671 words
On delay time delay apparatus comprising, in combination, first lead means adapted to be connected to one side of a single phase alternating current line, second lead means adapted to be connected to the other side of said single phase alternating current line, a full-wave rectifier having one input terminal thereof directly connected to the second lead means, the fullwave rectifier being adapted to have the other input terminal thereof connected by way of a relay coil to the first lead means, a normally nonconductive controlled rectifier having the anodecathode path thereof connected across the output leads of the full-wave rectifier and while conductive providing a closed switch whereby sufficient current from the alternating current line flows through the relay coil to actuate the relay, a small current insufficient to actuate the relay flowing through the relay coil before the controlled rectifier is gated-on, an R-C timing circuit including in series a first resistor, a timing capacitor and an adjustable timing resistor connected across the output of the full-wave rectifier, a trigger circuit including a pair of complementary NPN and PNP transistors, each of the transistors having a base, emitter and collector, the base of the PNP transistor being connected to the junction between the timing capacitor and the timing resistor and to the collector of the NPN transistor and the collector of the PNP transistor being connected to the base of the NPN transistor and by a resistance to the cathode of the controlled rectifier, the emitter of the NPN transistor being connected to the control element of the controlled rectifier to supply a gating signal thereto when the complementary transistors are conductive, the threshold level at which the complementary transistors become conductive being established by threshold level determining circuit means including in series a first Zener diode, a first diode rectifier, the emitter-base junction of the PNP transistor and a second resistor connected from the junction between the first Zener diode and the first diode rectifier to the cathode of said controlled rectifier, the last named circuit means being connected in parallel with the timing capacitor, said timing capacitor being normally discharged at the connecting moment when the first lead means and the second lead means are first connected to the alternating current line whereby the complementary transistors are nonconductive and no gate signal is supplied to the controlled rectifier thereby providing that the controlled rectifier is nonconductive, the connection of the first lead means and second lead means to the single phase alternating current line causing a small current to flow through the relay coil and the second lead means into the full-wave rectifier and to develop a full-wave rectified direct current output voltage thereacross, said full-wave rectified output current flowing through the first resistor and starting to flow into said timing capacitor, said timing capacitor after a preselected time interval being charged to a sufficient voltage to equal the threshold voltage as determined by the threshold level determining circuit means and causing the complementary transistors to conduct thereby causing the trigger circuit to supply a gating signal to the controlled rectifier, the gating signal causing the controlled rectifier to assume a conductive condition thereby causing a relay-actuating current to flow through the relay coil, resistance circuit means including third and fourth resistors both having one end thereof operatively connected to the first lead means, said third resistor having the other end thereof operatively connected to the anode of the controlled rectifier, said fourth resistor having the other end thereof operatively connected to the cathode of the controlled rectifier, said resistance circuit means obtaining a pulsating direct current with a substantially 90 electrical degree phase difference with respect to the current in the relay coil and applying said pulsating direct current to the controlled rectifier whereby current through the controlled rectifier never decreases below its holding current and the controlled rectifier is maintained in a conductive condition with full actuating current through the relay coil until the electrical circuit is broken at the first and second lead means.
Claim 2
Dependent Claim 671 words
On delay time delay apparatus comprising, in combination, first lead means adapted to be connected to one side of a single phase alternating current line, second lead means adapted to be connected to the other side of said single phase alternating current line, a full-wave rectifier having one input terminal thereof directly connected to the second lead means, the fullwave rectifier being adapted to have the other input terminal thereof connected by way of a relay coil to the first lead means, a normally nonconductive controlled rectifier having the anodecathode path thereof connected across the output leads of the full-wave rectifier and while conductive providing a closed switch whereby sufficient current from the alternating current line flows through the relay coil to actuate the relay, a small current insufficient to actuate the relay flowing through the relay coil before the controlled rectifier is gated-on, an R-C timing circuit including in series a first resistor, a timing capacitor and an adjustable timing resistor connected across the output of the full-wave rectifier, a trigger circuit including a pair of complementary NPN and PNP transistors, each of the transistors having a base, emitter and collector, the base of the PNP transistor being connected to the junction between the timing capacitor and the timing resistor and to the collector of the NPN transistor and the collector of the PNP transistor being connected to the base of the NPN transistor and by a resistance to the cathode of the controlled rectifier, the emitter of the NPN transistor being connected to the control element of the controlled rectifier to supply a gating signal thereto when the complementary transistors are conductive, the threshold level at which the complementary transistors become conductive being established by threshold level determining circuit means including in series a first Zener diode, a first diode rectifier, the emitter-base junction of the PNP transistor and a second resistor connected from the junction between the first Zener diode and the first diode rectifier to the cathode of said controlled rectifier, the last named circuit means being connected in parallel with the timing capacitor, said timing capacitor being normally discharged at the connecting moment when the first lead means and the second lead means are first connected to the alternating current line whereby the complementary transistors are nonconductive and no gate signal is supplied to the controlled rectifier thereby providing that the controlled rectifier is nonconductive, the connection of the first lead means and second lead means to the single phase alternating current line causing a small current to flow through the relay coil and the second lead means into the full-wave rectifier and to develop a full-wave rectified direct current output voltage thereacross, said full-wave rectified output current flowing through the first resistor and starting to flow into said timing capacitor, said timing capacitor after a preselected time interval being charged to a sufficient voltage to equal the threshold voltage as determined by the threshold level determining circuit means and causing the complementary transistors to conduct thereby causing the trigger circuit to supply a gating signal to the controlled rectifier, the gating signal causing the controlled rectifier to assume a conductive condition thereby causing a relay-actuating current to flow through the relay coil, resistance circuit means including third and fourth resistors both having one end thereof operatively connected to the first lead means, said third resistor having the other end thereof operatively connected to the anode of the controlled rectifier, said fourth resistor having the other end thereof operatively connected to the cathode of the controlled rectifier, said resistance circuit means obtaining a pulsating direct current with a substantially 90 electrical degree phase difference with respect to the current in the relay coil and applying said pulsating direct current to the controlled rectifier whereby current through the controlled rectifier never decreases below its holding current and the controlled rectifier is maintained in a conductive condition with full actuating current through the relay coil until the electrical circuit is broken at the first and second lead means.
Claim 3
Dependent Claim 71 words
On delay time delay apparatus according to claim 1 including in addition a second Zener diode connected in shunt with that portion of the R-C timing circuit consisting of the timing capacitor and the timing resistor, the second Zener diode clamping the voltage across the timing capacitor and timing resistor at a predetermined value thereby providing a charging voltage substantially independent of fluctuations in the output voltage of the full-wave rectifier.
Claim 4
Dependent Claim 36 words
On delay time delay apparatus according to claim 1 including in addition a fifth resistor and a second capacitor connected in series across the output of the full-wave rectifier to filter the full rectified output therefrom.
Claim 5
Dependent Claim 32 words
On delay time delay apparatus according to claim 1 including in addition a further Zener diode connected across the anode-cathode path of the controlled rectifier to protect the controlled-rectifier from voltage transients.
Claim 6
Dependent Claim 177 words
Apparatus according to claim 1 in which the full-wave rectifier is additionally characterized as having a positive output lead and a negative output lead, A fifth resistor connected in series between the fourth resistor and the negative lead of the full-wave rectifier, said negative lead being connected to the cathode of the controlled rectifier, a second diode having the anode thereof connected to the junction between the fourth and fifth resistors and having the cathode thereof connected to the junction between the timing capacitor and the timing resistor, and a third diode and a sixth resistor connecting the other terminal of the timing capacitor to said positive output lead of the full-wave rectifier whereby when the controlled rectifier is gated-on a current path for quickly discharging the timing capacitor is provided through the controlled rectifier, said last-named current path from one terminal of the charging capacitor to the controlled rectifier including the third diode and sixth resistor, said last-named current path from the charging capacitor to the controlled rectifier including said second diode and said fifth resistor.
Claim 7
Dependent Claim 107 words
On delay time delay apparatus according to claim 1 including circuit means for resetting the circuit to its initial condition if the alternating current line voltage is interrupted prior to the completion of the timing operation, the circuit means including a second diode having its anode connected to the fourth resistor and its cathode connected to the junction between the timing capacitor and the timing resistor, and a third diode and a fifth resistor in series therewith connected across the first resistor, said quick discharging current path including the first resistor, the third diode and fifth resistor, the third resistor, the fourth resistor and the second diode.
Claim 8
Dependent Claim 74 words
On delay time delay apparatus according to claim 5 in which a pulsating direct current voltage applied across said fifth resistor causes positive pulses to be applied to the anode of the second diode having the cathode thereof connected to the junction between the timing capacitor and the timing resistor thereby causing discharging pulses to be applied to the timing capacitor with the result that the timing capacitor resets much closer to zero voltage.
Claim 9
Dependent Claim 27 words
On delay time delay apparatus according to claim 5 in which said second diode provides a current path which shorts the timing resistor during the resetting process.
Claim 10
Dependent Claim 32 words
Apparatus according to claim 3 in which the filter capacitor across the output of the full-wave rectifier has a value selected whereby the last-named capacitor also serves as a dv/dt suppressor capacitor.
Claim 11
Dependent Claim 278 words
In on delay time delay apparatus of the type in which first and second leads are adapted to be connected to a single phase alternating current line to initiate a timing operation, in which a full-wave rectifier is adapted to have the input thereof connected between leads, by way of a relay coil, said full-wave rectifier having the anode and cathode of a controlled rectifier connected across the output of the full-wave rectifier, full relay coil current flowing therethrough when the controlled rectifier connected across the output terminals of the full-wave rectifier is gated-on, the improvement which comprises a time delay trigger circuit not requiring a well regulated direct current supply interposed between the output of the full-wave rectifier and the control element of the controlled rectifier, said trigger circuit including a timing capacitor and timing resistor, and Zener diode means operatively connected to the full-wave rectifier for providing a clamped voltage for application to the timing capacitor, said clamped voltage being a voltage substantially less than the peak output voltage of the full-wave rectifier whereby the clamped voltage is substantially unaffected by variations in the output of the full-wave rectifier, the trigger circuit including a complementary pair of transistors switched on when the voltage on the timing capacitor is equal to a predetermined threshold value determined in part by the voltage drop across the emitter-base junction of one transistor of the pair of transistors, the trigger circuit interconnecting the timing capacitor to the controlled rectifier to supply a gating signal to the controlled rectifier to fire the controlled rectifier a predetermined time interval after the on delay time delay apparatus is connected to an alternating current line.
Claim 12
Dependent Claim 278 words
In on delay time delay apparatus of the type in which first and second leads are adapted to be connected to a single phase alternating current line to initiate a timing operation, in which a full-wave rectifier is adapted to have the input thereof connected between leads, by way of a relay coil, said full-wave rectifier having the anode and cathode of a controlled rectifier connected across the output of the full-wave rectifier, full relay coil current flowing therethrough when the controlled rectifier connected across the output terminals of the full-wave rectifier is gated-on, the improvement which comprises a time delay trigger circuit not requiring a well regulated direct current supply interposed between the output of the full-wave rectifier and the control element of the controlled rectifier, said trigger circuit including a timing capacitor and timing resistor, and Zener diode means operatively connected to the full-wave rectifier for providing a clamped voltage for application to the timing capacitor, said clamped voltage being a voltage substantially less than the peak output voltage of the full-wave rectifier whereby the clamped voltage is substantially unaffected by variations in the output of the full-wave rectifier, the trigger circuit including a complementary pair of transistors switched on when the voltage on the timing capacitor is equal to a predetermined threshold value determined in part by the voltage drop across the emitter-base junction of one transistor of the pair of transistors, the trigger circuit interconnecting the timing capacitor to the controlled rectifier to supply a gating signal to the controlled rectifier to fire the controlled rectifier a predetermined time interval after the on delay time delay apparatus is connected to an alternating current line.
Claim 13
Dependent Claim 79 words
On delay time delay apparatus according to claim 2 including in addition filter means for the full-wave rectifier, circuit means for diverting the current which flows through the second Zener diode which clamps the charging voltage for the timing capacitor at a predetermined value during the timing operation thereafter into the control element of the controlled rectifier to thereby reduce the current drain on the filter of the full-wave rectifier required to supply gating current for the controlled rectifier.
Claim 14
Dependent Claim 47 words
On delay time delay apparatus according to claim 1 including an additional capacitor connected from the base of the PNP transistor to the junction between the first diode and the first Zener diode for reducing the high frequency noise voltage sensitivity of said complementary pair of transistors.

References Cited (Backward Citations)

US3146392A Cited
US3210605A Cited
US3250891A Cited
US3355632A Cited
US3414766A Cited
US3486041A Cited
US3478250A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-06-07 1974-12-07 1975-06-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-06-07 1978-12-07 1979-06-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-06-07 1982-12-07 1983-06-08 $7700.00 Window Closed / Lapsed

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